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| W90P710 32-BIT ARM7TDMI-BASED MCU W90P710 16/32-bit ARM microcontroller Product Data Sheet -1- Publication Release Date: January 17, 2005 Revision A.1 W90P710 Revision History REVISION DATE COMMENTS A A.1 A.2 2005/12/02 2005/12/21 2006/01/17 Draft Modify the register definition Modify SDIO description -2- W90P710 Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 6 FEATURES ................................................................................................................................. 6 PIN DIAGRAM .......................................................................................................................... 13 PIN ASSIGNMENT ................................................................................................................... 14 PIN DESCRIPTION................................................................................................................... 20 BLOCK DIAGRAM .................................................................................................................... 33 FUNCTIONAL DESCRIPTION ................................................................................................. 34 7.1 7.2 ARM7TDMI CPU CORE ............................................................................................... 34 System Manager........................................................................................................... 35 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 Overview ........................................................................................................................35 System Memory Map......................................................................................................35 Address Bus Generation ................................................................................................38 Data Bus Connection with External Memory ..................................................................38 Bus Arbitration................................................................................................................47 Power management .......................................................................................................48 Power-On Setting ...........................................................................................................50 System Manager Control Registers Map ........................................................................51 EBI Overview..................................................................................................................65 SDRAM Controller ..........................................................................................................65 EBI Control Registers Map .............................................................................................69 On-Chip RAM .................................................................................................................87 Non-Cacheable Area ......................................................................................................87 Instruction Cache............................................................................................................88 Data Cache ....................................................................................................................90 Write Buffer ....................................................................................................................92 Cache Control Registers Map.........................................................................................92 EMC Functional Description ...........................................................................................99 EMC Register Mapping ................................................................................................109 GDMA Functional Description ......................................................................................162 GDMA Register Map ....................................................................................................163 USB Host Functional Description .................................................................................172 USB Host Controller Registers Map .............................................................................173 7.3 External Bus Interface .................................................................................................. 65 7.3.1 7.3.2 7.3.3 7.4 Cache Controller........................................................................................................... 87 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 Ethernet MAC Controller............................................................................................... 98 7.5.1 7.5.2 7.6 GDMA Controller ........................................................................................................ 162 7.6.1 7.6.2 7.7 USB Host Controller ................................................................................................... 172 7.7.1 7.7.2 -3- Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.7.3 7.7.4 7.7.5 HCCA ...........................................................................................................................195 Endpoint Descriptor ......................................................................................................195 Transfer Descriptor.......................................................................................................195 USB Endpoints .............................................................................................................196 Standard device request...............................................................................................196 USB Device Register Description .................................................................................196 Functional Description ..................................................................................................235 Register Mapping .........................................................................................................237 SDIO Register Description ...........................................................................................238 Main Features ............................................................................................................254 LCD Register MAP .....................................................................................................255 LCD Special Register Description ..............................................................................257 IIS Interface ................................................................................................................296 AC97 Interface ...........................................................................................................297 Audio Controller Register Map....................................................................................301 UART0........................................................................................................................322 UART1........................................................................................................................322 UART2........................................................................................................................324 UART3........................................................................................................................326 General UART Controller ...........................................................................................327 High speed UART Controller ......................................................................................341 General Timer Controller ............................................................................................355 Watchdog Timer .........................................................................................................355 Timer Control Registers Map......................................................................................355 Interrupt Sources ........................................................................................................364 AIC Registers Map .....................................................................................................367 GPIO Control Registers Map......................................................................................383 GPIO Register Description .........................................................................................384 RTC Register Map......................................................................................................417 Register Mapping .......................................................................................................430 7.8 USB Device Controller................................................................................................ 195 7.8.1 7.8.2 7.8.3 7.9 SDIO Host Controller .................................................................................................. 235 7.9.1 7.9.2 7.9.3 7.10 LCD Controller ............................................................................................................ 254 7.10.1 7.10.2 7.10.3 7.11 Audio Controller .......................................................................................................... 296 7.11.1 7.11.2 7.11.3 7.12 Universal Asynchronous Receiver/Transmitter Controller ......................................... 320 7.12.1 7.12.2 7.12.3 7.12.4 7.12.5 7.12.6 7.13 Timer/Watchdog Controller......................................................................................... 355 7.13.1 7.13.2 7.13.3 7.14 Advanced Interrupt Controller..................................................................................... 363 7.14.1 7.14.2 7.15 General-Purpose Input/Output ................................................................................... 380 7.15.1 7.15.2 7.16 7.17 Real Time Clock ......................................................................................................... 415 7.16.1 7.17.1 Smart Card Host Interface .......................................................................................... 430 -4- W90P710 7.17.2 7.17.3 Register Description ...................................................................................................432 Functional description.................................................................................................457 I2C Protocol ................................................................................................................461 I2C Serial Interface Control Registers Map ................................................................464 USI Timing Diagram ...................................................................................................471 USI Registers Map .....................................................................................................472 PWM double buffering and reload automatically ........................................................479 Modulate Duty Ratio ...................................................................................................480 Dead Zone Generator.................................................................................................480 PWM Timer Start procedure.......................................................................................481 PWM Timer Stop procedure .......................................................................................481 PWM Register Map ....................................................................................................482 KeyPad Interface Register Map..................................................................................491 Register Description ...................................................................................................492 PS2 Host Controller Interface Register Map...............................................................500 Register Description ...................................................................................................500 7.18 I2C Interface ............................................................................................................... 460 7.18.1 7.18.2 7.19 Universal Serial Interface............................................................................................ 471 7.19.1 7.19.2 7.20 PWM ........................................................................................................................... 479 7.20.1 7.20.2 7.20.3 7.20.4 7.20.5 7.20.6 7.21 Keypad Interface......................................................................................................... 490 7.21.1 7.21.2 7.22 PS2 Host Interface Controller ..................................................................................... 499 7.22.1 7.22.2 8. 9. 10. ELECTRICAL SPECIFICATIONS........................................................................................... 504 PACKAGE SPECIFICATIONS................................................................................................ 504 APPENDIX A: W90P710 REGISTERS MAPPING TABLE..................................................... 505 -5- Publication Release Date: January 17, 2005 Revision A.2 W90P710 1. GENERAL DESCRIPTION The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost sensitive and power sensitive applications. One 10/100 Mb MAC of Ethernet controller is built-in to reduce total system cost. A LCD controller is also built-in to support TFT and low cost STN LCD modules. With one USB 1.1 host controller, one USB 1.1 device controller, two smart card host controller, four independent UARTs, one Watchdog timer, up to 71 programmable I/O ports, PS/2 keyboard controller and an advanced interrupt controller, the W90P710 is particularly suitable for point-of-sale (POS), access control and data collector. The W90P710 also provides one AC97/IS controller, one SD/SDIO host controller, one 2-Channel GDMA, two 24-bit timers with 8-bit pre-scale, The external bus interface (EBI) controller provides for SDRAM, ROM/SRAM, flash memory and I/O devices. The System Manager includes an internal 32-bit system bus arbiter and a PLL clock controller. With a wide range of serial communication and Ethernet interfaces, the W90P710 is also suitable for communication gateways as well as many other general purpose applications. 2. FEATURES Architecture Fully 16/32-bit RISC architecture Little/Big-Endian mode supported Efficient and powerful ARM7TDMI core Cost-effective JTAG-based debug solution External Bus Interface 8/16/32-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os Support for SDRAM Programmable access cycle (0-7 wait cycle) Four-word depth write buffer for SDRAM write data Cost-effective memory-to-peripheral DMA interface Instruction and Data Cache Two-way, Set-associative, 4K-byte I-cache and 4K-byte D-cache Support for LRU (Least Recently Used) Protocol Cache can be configured as internal SRAM Support Cache Lock function -6- W90P710 Ethernet MAC Controller DMA engine with burst mode MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) Data alignment logic Endian translation 100/10-Mbit per second operation Full compliance with IEEE standard 802.3 RMII interface only Station Management Signaling On-Chip CAM (up to 16 destination addresses) Full-duplex mode with PAUSE feature Long/short packet modes PAD generation Color LCD Controller (CLCDC) (1) STN LCD Display Supports Sync-type STN LCD Supports 2 types of LCD panels: 4-bit single scan, and 8-bit single scan display type Supports 16 gray levels for Monochrome STN LCD panel Supports 4096 color for Color STN LCD panel Virtual coloring method: Frame Rate Control (16-level) Anti-flickering method: Time-based Dithering (2) TFT LCD Display Supports Sync-type TFT LCD and Sync-type High-color TFT LCD Supports 8-bpp(RGB332) palette color display Supports 12-bpp(RGB444)/16-bpp (RGB565)/18-bpp(RGB666) non-palette true color display (3) TV Encoder Supports 8-bit YCbCr data output format to connect with external TV Encoder (4) LCD Preprocessing Image resize - Horizontal/Vertical Down-Scaling - Horizontal/Vertical Up-Scaling Image relocation - Horizontal /Vertical Cropping - Virtual Display -7- Publication Release Date: January 17, 2005 Revision A.2 W90P710 (5) LCD Post processing Support for one OSD overlay Support various OSD function (6) Others Color-look up table size 256x32 bit for TFT used Dedicated DMA for block transfer mode DMA Controller 2-channel General DMA for memory-to-memory data transfers without CPU intervention Initialed by a software or external DMA request Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers 4-data burst mode UART Four UART (serial I/O) blocks with interrupt-based operation Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive Programmable baud rates 1, 1/2 or 2 stop bits Odd or even parity Break generation and detection Parity, overrun and framing error detection X16 clock mode UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR Timers Two programmable 24-bit timers with 8-bit pre-scaler One programmable 20 bit with selectable additional 8-bit prescaler Watchdog timer One-shot mode, periodical mode or toggle mode operation Programmable I/Os 71 programmable I/O ports Pins individually configurable to input, output or I/O mode for dedicated signals I/O ports are configurable for Multiple functions -8- W90P710 Advanced Interrupt Controller 31 interrupt sources, including 6 external interrupt sources Programmable normal or fast interrupt mode (IRQ, FIQ) Programmable as either edge-triggered or level-sensitive for 6 external interrupt sources Programmable as either low-active or high-active for 6 external interrupt sources Priority methodology is encoded to allow for interrupt daisy-chaining Automatically mask out the lower priority interrupt during interrupt nesting USB Host Controller USB 1.1 compliant Compatible with Open HCI 1.0 specification Supports low-speed and full speed devices Build-in DMA for real time data transfer Two on-chip USB transceivers with one optionally shared with USB Device Controller USB Device Controller USB 1.1 compliant Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich USB functions Two PLLs The external clock can be multiplied by on-chip PLL to provide high frequency system clock The input frequency range is 3-30MHz; 15MHz is preferred. One PLL for both CPU and USB host/device controller One PLL for LCD pixel clock and audio IIS 12.288/16.934MHz clock source Programmable clock frequency Real Time Clock (RTC) 32.768KHz operation Time counter (second, minute, hour) and calendar counter (day, month, year) Alarm register (second, minute, hour, day, month, year) 12 or 24-hour mode selectable Recognize leap year automatically Day of the week counter Frequency compensate register (FCR) Beside FCR, all clock and alarm data expressed in BCD code Support tick time interrupt Publication Release Date: January 17, 2005 Revision A.2 -9- W90P710 4-Channel PWM Four 16-bit timers with PWM Two 8-bit pre-scalers & Two 4-bit dividers Programmable duty control of output waveform (PWM) Auto reload mode or one-shot pulse mode Dead-zone generator I2C Master 2-Channel I2C Compatible with Philips I2C standard, support master mode only Support multi master operation Clock stretching and wait state generation Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer Software programmable acknowledge bit Arbitration lost interrupt, with automatic transfer cancellation Start/Stop/Repeated Start/Acknowledge generation Start/Stop/Repeated Start detection Bus busy detection Supports 7 bit addressing mode Software mode I2C Universal Serial Interface (USI) 1-Channel USI Support USI (Microwire/SPI) master mode Full duplex synchronous serial data transfer Variable length of transfer word up to 32 bits Provide burst mode operation, transmit/receive can be executed up to four times in one transfer MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Two slave/device select lines Fully static synchronous design with one clock domain 2-Channel AC97/I2S Audio Codec Host Interface AHB master port and an AHB slave port are offered in audio controller. Always 8-beat incrementing burst Always bus lock when 8-beat incrementing burst - 10 - W90P710 When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically Smart Card Host Interface (SCHI) ISO-7816 compliant PC/SC T=0, T=1 compliant 16-byte transmitter FIFO and 16-byte receiver FIFO FIFO threshold interrupt to optimize system performance Programmable transmission clock frequency Versatile baud rate configuration UART-like register file structure General-purpose C4, C8 channels SD/SDIO Host Interface Directly connect to Secure Digital (SD, MMC or SDIO) flash memory card. Supports DMA function to accelerate the data transfer between the internal buffer, external SDRAM, and flash memory card. Two 512 bytes internal buffers are embedded inside the controller. No SPI mode. KeyPad Scan Interface Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4x8 array without auxiliary component Programmable debounce time One or two keys scan with interrupt and three keys reset function. Wakeup CPU from IDEL/Power Down mode PS2 Host Interface APB slave consisted of PS2 protocol. Connect IBM keyboard or bar-code reader through PS2 interface. Provide hardware scan code to ASCII translation Power management Programmable clock enables for individual peripheral IDLE mode to halt ARM Core and keep peripheral working Power-Down mode to stop all clocks included external crystal oscillator. Exit IDLE by all interrupts Exit Power-Down by keypad,USB device and external interrupts - 11 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Operation Voltage Range 3.0 ~ 3.6 V for IO Buffer 1.62 ~ 1.98 V for Core Logic Operation Temperature Range TBD Operating Frequency Up to 80 MHz Package Type 176-pin LQFP - 12 - W90P710 10 15 20 25 30 35 3. PIN DIAGRAM USB1VDD DP1 DN1 USB1VSS USB0VSS DN0 DP0 USB0VDD VDD33 TXD0/GPIO[5] RXD0/GPIO[6] TXD1/GPIO[7] RXD1/GPIO[8] CTS1/TXD2(IrDA)/PS2_CLK/GPIO[9] RTS1/RXD2(IrDA)/PS2_DATA/GPIO[10] VSS33 SCL0/SFRM/TIMER0/GPIO[11] SDA0/SSPTXD/TIMER1/GPIO[12] SCL1/SCLK/KPI_ROW[3]/GPIO[13] SDA1/SSPRXD/KPI_ROW[2]/GPIO[14] VDD18 VSS18 KPI_ROW[0]/VCLK/GPIO[30] KPI_ROW[1]/VDEN/GPIO[31] KPI_ROW[2]/VSYNC/GPIO[32] KPI_ROW[3]/HSYNC/GPIO[33] KPI_COL[7]/VD[7]/GPIO[41] KPI_COL[6]/VD[6]/GPIO[40] KPI_COL[5]/VD[5]/GPIO[39] KPI_COL[4]/VD[4]/GPIO[38] KPI_COL[3]/VD[3]/GPIO[37] KPI_COL[2]/VD[2]/GPIO[36] KPI_COL[1]/VD[1]/GPIO[35] KPI_COL[0]/VD[0]/GPIO[34] VDD33 VSS33 nRESET TEST PLL0VDD18 PLL0VSS18 PLL1VSS18 PLL1VDD18 nIRQ[0]/GPIO[16] nIRQ[1]/GPIO[17] 40 nBTCS MCKE nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nWE nWBE[0]/SDQM[0] nWBE[1]/SDQM[1] nWBE[2]/SDQM[2]/GPIO[69] nWBE[3]/SDQM[3]/GPIO[68] nIRQ[2]/GPIO[18] nIRQ[3]/GPIO[19] D[23]/VD[15]/GPIO[59] D[22]/VD[14]/GPIO[58] D[21]/VD[13]/GPIO[57] D[20]/VD[12]/GPIO[56] D[19]/VD[11]/GPIO[55] D[18]/VD[10]/GPIO[54] D[17]/VD[9]/GPIO[53] D[16]/VD[8]/GPIO[52] VSS18 D[15]/TBUS[15] D[14]/TBUS[14] VDD18 D[13]/TBUS[13] D[12]/TBUS[12] D[11]/TBUS[11] D[10]/TBUS[10] VDD33 D[9]/TBUS[9] D[8]/TBUS[8] D[7]/TBUS[7] D[6]/TBUS[6] D[5]/TBUS[5] VSS33 D[4]/TBUS[4] D[3]/TBUS[3] D[2]/TBUS[2] D[1]/TBUS[1] D[0]/TBUS[0] 135 100 140 145 85 80 W90P710 75 150 70 65 160 60 165 55 170 50 175 5 - 13 - 155 PHY_MDC/GPIO[51]/KP_ROW[1]/VD[17] PHY_MDIO/GPIO[50]/KPI_ROW[0]/VD[16] PHY_TXD[1]/GPIO[49]/KPI_COL[7]/VD[15] VDD33 PHY_TXD[0]/GPIO[48]/KPI_COL[6]/VD[14] PHY_TXEN/GPIO[47]/KPI_COL[5]/VD[13] PHY_REFCLK/GPIO[46]/KPI_COL[4]/VD[12] PHY_RXD[1]/GPIO[45]/KPI_COL[3]/VD[11] VSS33 PHY_RXD[0]/GPIO[44]/KPI_COL[2]/VD[10] PHY_CRSDV/GPIO[43]/KPI_COL[1]/VD[9] PHY_RXERR/GPIO[42]/KPI_COL[0]/VD[8] SC1_PWR/nXDACK/VD[8]/GPIO[20] SC1_PRES/nXDREQ/VD[9]GPIO[21] SC1_RST/SD_CD/VD[10]/GPIO[22] VSS33 SC1_CLK/SD_PWR/VD[11]/GPIO[23] SC1_DAT/SD_DAT3/VD[12]/GPIO[24] SC0_PWR/SD_DAT2/VD[13]/GPIO[25] VDD33 SC0_PRES/SD_DAT1/VD[14]/GPIO[26] SC0_RST/SD_DAT0/VD[15]/GPIO[27] SC0_CLK/SD_CLK/VD[16]/GPIO[28] SC0_DAT/SD_CMD/VD[17]/[GPIO[29] VSS18 VDD18 AC97_BITCLK/I2S_BITCLK/PWM[3]/RXD3/GPIO[4] AC97_SYNC/I2S_LRCLK/PWM[2]/TXD3/GPIO[3] AC97_DATAO/I2S_DATAO/PWM[1]/DSR3/GPIO[2] AC97_DATAI/I2S_DATAI/PWM[0]/DTR3/GPIO[1] AC97_nRESET/I2S_MCLK/GPIO[0] XTAL(32768) EXTAL(32768) RTCVDD18 VDD33 XTAL(15M) EXTAL(15M) VSS33 nWDOG/GPIO[15] nTRST TCK TDO TDI TMS 176 -pin LQFP Fig 3.1 Pin Diagram Publication Release Date: January 17, 2005 Revision A.2 110 105 95 90 125 130 120 115 nWAIT/TREQB nOE nECS[0] nECS[1] nECS[2] VDD33 VSS33 nECS[3] D[24]/VD[16]/GPIO[60] D[25]/VD[17]/GPIO[61] D[26]/VD[18]/GPIO[62] D[27]/VD[19]/GPIO[63] VDD33 D[28]/VD[20]/GPIO[64] D[29]/VD[21]/GPIO[65] D[30]/VD[22]/GPIO[66] D[31]/VD[23]/GPIO[67] A[21] VSS33 A[20] A[19] A[18] A[17]/TREQA VDD18 A[16]/TACK A[15]/TBUS[31] A[14]/TBUS[30] VSS18 A[13]/TBUS[29] A[12]/TBUS[28] A[11]/TBUS[27] A[10]/TBUS[26] VDD33 A[9]/TBUS[25] A[8]/TBUS[24] A[7]/TBUS[23] A[6]/TBUS[22] A[5]/TBUS[21] VSS33 A[4]/TBUS[20] A[3]/TBUS[19] A[2]/TBUS[18] A[1]/TBUS[17] A[0]/TBUS[16] W90P710 4. PIN ASSIGNMENT Table 4.1 W90P710 Pins Assignment PIN NAME 176-PIN LQFP Clock & Reset EXTAL (15M) XTAL (15M) EXTAL (32768) XTAL (32768) nRESET JTAG Interface TMS TDI TDO TCK nTRST External Bus Interface A [21] A [20:0] D [31:16] / VD [23:8] / GPIO [67:52] D [15:0] nWBE [3:2] / SDQM [3:2] / GPIO[69:68] nWBE [1;0] / SDQM [1:0] nSCS [1:0] nSRAS nSCAS MCKE nSWE MCLK nWAIT/ GPIO[70] / nIRQ5 nBTCS nECS [3] nECS [2:0] nOE ( 5 pins ) 52 53 57 56 37 ( 5 pins ) 45 46 47 48 49 ( 72 pins ) 115 113-110,108-106, 104-101,99-95, 93-89 116-119,121-124, 149-156 158,159,161-164, 166-170,172-176 146,145 144,143 136,135 137 138 134 142 140 132 133 125 128-130 131 - 14 - W90P710 Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP Ethernet Interface PHY_MDC / GPIO [51] / KPROW[1] / LCD_ VD[17] PHY_MDIO / GPIO [50] / KPROW[0] / LCD_LD[16] PHY_TXD [1:0] / GPIO[49:48] / KPCOL[7:6] / LCD_VD[15:14] PHY_TXEN / GPIO [47] / KPCOL[5] / LCD_VD[13] PHY_REFCLK / GPIO [46] / KPCOL[4] / LCD_VD[12] PHY_RXD [1:0] / GPIO [45:44] / KPCOL[3:2] / LCD_VD[11:10] PHY_CRSDV / GPIO [43] / KPCOL[1] / LCD_VD[9] PHY_RXERR / GPIO [42] / KPCOL[0] / LCD_VD[8] AC97/I2S/PWM/UART3 AC97_nRESET / I2S_MCLK / GPIO [0] / USB_PWREN ( 10 pins ) 88 87 86,84 83 82 81,79 78 77 ( 5 pins ) 58 - 15 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP AC97/I2S/PWM/UART3 AC97_DATAI / I2S_DATAI / PWM [0] / DTR3 / GPIO [1] AC97_DATAO / I2S_DATAO / PWM [1] / DSR3 / GPIO [2] AC97_SYNC / I2S_LRCLK / PWM [2] / TXD3 / GPIO [3] AC97_BITCLK / I2S_BITCLK / PWM [3] / RXD3 GPIO [4] USB Interface DP0 DN 0 DP1 DN1 Miscellaneous nIRQ [3:2] / GPIO [19:18] nIRQ [1] / GPIO [17 / USB_OVRCUR nIRQ [0] / GPIO [16] nWDOG / GPIO [15] / USB_PWREN RTCVDD18 ( 5 pins ) 59 60 61 62 ( 4 pins ) 7 6 2 3 ( 7 pins ) 148,147 44 43 50 55 - 16 - W90P710 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP I2C/USI(SPI/MW) SCL0 / SFRM / Timer0 / GPIO [11] SDA0 / SSPTXD / Timer1 / GPIO [12] SCL1 / SCLK / GPIO [13] / KPROW[3] SDA1 / SSPRXD / GPIO [14] / KPROW[2] UART0/UART1/UART2/PS2 TXD0 / GPIO [5] RXD0 / GPIO [6] TXD1 / GPIO [7] RXD1 / GPIO [8] CTS1 / TXD2(IrDA) / PS2_CLK / GPIO [9] RTS1 / RXD2(IrDA) / PS2_DATA / GPIO [10] ( 4 pins ) 17 18 19 20 ( 6 pins ) 10 11 12 13 14 15 - 17 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP SCHI/SDIO/XDMA SC0_DAT / SD_CMD / GPIO [29] / LCD_VD[17] SC0_CLK / SD_CLK / GPIO [28] / LCD_VD[16] SC0_RST / SD_DAT0 / GPIO [27] / LCD_VD[15] SC0_PRES / SD_DAT1 / GPIO [26] / LCD_VD[14] SC0_PWR / SD_DAT2 / GPIO [25] / LCD_VD[13] SC1_DAT / SD_DAT3 / GPIO [24] / LCD_VD[12] SC1_CLK / GPIO [23] / LCD_VD[11] SC1_RST / SD_CD / GPIO [22] / LCD_VD[10] SC1_PRES / nXDREQ / GPIO [21] / LCD_VD[9] SC1_PWR / nXDACK / GPIO [20] / LCD_VD[8] ( 10 pins ) 65 66 67 68 70 71 72 74 75 76 - 18 - W90P710 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP CLCDC VD[7:0] / GPIO [41:34] HSYNC / GPIO [33] VSYNC / GPIO [32] VDEN / GPIO [31] VCLK / GPIO [30] Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS PLLVDD18 PLLVSS18 ( 12 pins ) 27-34 26 25 24 23 ( 36 pins ) 21,63,109,160 22,38,64,105,157 9,35,54,69,85,100, 120,127,139,165 16,36,51,73,80,94, 114,126,141,171 1,8 4,5 39,42 40,41 - 19 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 5. PIN DESCRIPTION Table 5.1 W90P710 Pins Description PIN NAME Clock & Reset IO TYPE I O I O IS IDS IUS IUS O IUS O IOS IO IOS IOS O O O O O O DESCRIPTION 15MHz External Clock / Crystal Input 15MHz Crystal Output 32768Hz External Clock / Crystal Input(for RTC) 32768Hz Crystal Output(for RTC) System Reset, active-low JTAG Test Clock, internal pull-down with 58K ohm JTAG Test Mode Select, internal pull-up with 70K ohm JTAG Test Data in, internal pull-up with 70K ohm JTAG Test Data out JTAG Reset, active-low, internal pull-up with 70K ohm Address Bus (MSB) of external memory and IO devices. Address Bus of external memory and IO devices. Data Bus (MSB) of external memory and IO device, internal pull-up with 70K ohm. General Programmable In/Out Port GPIO[67:52]. Data Bus (LSB) of external memory and IO device. Write Byte Enable for specific device (nECS [3:0]). Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low. General Programmable In/Out Port [69:68] SDRAM chip select for two external banks, active-low. Row Address Strobe for SDRAM, active-low. Column Address Strobe for SDRAM, active-low. SDRAM Write Enable, active-low SDRAM Clock Enable, active-high System Master Clock Out, SDRAM clock, output with slew-rate control External Wait, active-low. This pin indicates that the external devices need more active cycle during access operation. General Programmable In/Out Port GPIO[70]. If memory and IO devices in EBI do not need wait request, it can be configured as GPIO[7] or nIRQ5 ROM/Flash Chip Select, active-low. External I/O Chip Select, active-low. ROM/Flash, External Memory Output Enable, active-low. EXTAL (15M) XTAL (15M) EXTAL (32768) XTAL (32768) nRESET JTAG Interface TCK TMS TDI TDO nTRST External Bus Interface A [21:18] A [17:0] D [31:16] / VD[23:8] / GPIO [67:52] D [15:0] / nWBE [3:0] / SDQM [3:0] / GPIO[69:68] nSCS [1:0] nSRAS nSCAS nSWE MCKE MCLK nWAIT / GPIO[70] / nIRQ5 nBTCS nECS [3:0] nOE IUS O IO O - 20 - W90P710 Table 5.1 W90P710 Pins Description (Continued) Pin Name Ethernet Interface PHY_MDC / GPIO [51] / KPROW[1] / LCD_VD[17] PHY_MDIO / GPIO [50] / KPROW[0] / LCD_VD[16] PHY_TXD [1:0] / GPIO [49:48] / KPCOL[7:6] / LCD_VD[15] PHY_TXEN / GPIO [47] / KPCOL[5] / LCD_VD[14:13] PHY_REFCLK / GPIO [46] / KPCOL[4] / LCD_VD[12] PHY_RXD [1:0] / GPIO [45:44] / KPCOL[3:2] / LCD_VD[11:10] PHY_CRSDV / GPIO [43] / KPCOL[1] / LCD_VD[9] IO Type Description RMII Management Data Clock for Ethernet. It is the reference clock of MDIO. Each MDIO data will be latched at the rising edge of MDC clock. General Programmable In/Out Port [51] Keypad ROW[1] scan output. LCD VD[17] data output RMII Management Data I/O for Ethernet. It is used to transfer RMII control and status information between PHY and MAC. General Programmable In/Out Port [51] Keypad ROW[0] scan output. LCD VD[16] data output. 2-bit Transmit Data bus for Ethernet. General programmable In/Out Port [49:48] Keypad Column input [7:6], active low LCD VD[15] data output PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble and shall remain asserted while all di-bits to be transmitted are presented. Of course, it is synchronized with PHY_REFCLK. General Programmable In/Out Port [47] Keypad column input [5], active low LCD VD[14:13] data output. Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state. General Programmable In/Out port [46] Keypad column input [4], active low LCD VD[12] data output. 2-bit Receive Data bus for Ethernet. General Programmable In/Out Port [45:44] Keypad column input [3:2], active low LCD VD[11:10] data output. Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of PHY_CRSDV synchronous to the cycle of PHY_REFCLK, and only on 2-bit receive data boundaries. General Programmable In/Out port [43] Keypad column input [1], active low LCD VD[9] data output. Receive Data Error for Ethernet. It indicates a data error detected by PHY.The assertion should be lasted for longer than a period of PHY_REFCLK. When PHY_RXERR is asserted, the MAC will report a CRC error. General programmable In/Out port [42] Keypad column input [0], active low LCD VD[8] data output. IOU IO IOU IOU IOS IOS IOS PHY_RXERR / GPIO [42] / KPCOL[0] / LCD_VD[8] IOS - 21 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type Description AC97 CODEC Host Interface RESET Output. I2S CODEC Host Interface System Clock Output. General Purpose In/Out port [0] External interrupt request. USB host power enable output AC97 CODEC Host Interface Data Input. I2S CODEC Host Interface Data Input. PWM Channel 0 Output. Data Terminal Ready for UART4. General Purpose In /Out port [1] AC97 CODEC Host Interface Data Output. I2S CODEC Host Interface Data Output. PWM Channel 1 Output. Data Set Ready for UART4. General Purpose In/Out port [2] AC97 CODEC Host Interface Synchronous Pulse Output. I2S CODEC Host Interface Left/Right Channel Select Clock. PWM Channel 2 Output. Transmit Data for UART4. General Purpose In/Out port [3] AC97 CODEC Host Interface Bit Clock Input. I2S CODEC Host Interface Bit Clock. PWM Channel 3 Output. Receive Data for UART4. General Purpose In/Out port [4]. Differential Positive USB IO signal Differential Negative USB IO signal Differential Positive USB IO signal Differential Negative USB IO signal External Interrupt Request General Purpose I/O. External Interrupt Request General Purpose I/O nIRQ1 is used as USB host over-current detection input Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low General Purpose In/output USB host power switch enable output RTC independent battery power (1.8V) AC97/I2S/PWM/UART3 AC97_nRESET / I2S_MCLK / GPIO [0] / IOU nIRQ4 / USB_PWREN AC97_DATAI / I2S_DATAI / PWM [0] / IOU DTR4 / GPIO [1] AC97_DATAO / I2S_DATAO / PWM [1] / DSR4 / GPIO [2] AC97_SYNC / I2S_LRCLK / PWM [2] / TXD4 / GPIO [3] AC97_BITCLK / I2S_BITCLK / PWM [3] / RXD4 / GPIO [4] USB Interface DP0 DN0 DP1 DN1 Miscellaneous nIRQ [3:2] / GPIO [19:18] nIRQ [1:0] / GPIO [17:16] USB_OVRCUR nWDOG / GPIO [15] / USB_PWREN RTCVDD IOU P IOU IOU IOU IOS IO IO IO IO IOU - 22 - W90P710 Table 5.1 W90P710 Pins Description (Continued) Pin Name I2C/USI IO Type Description SCL0 / SFRM / IOU Timer0 / GPIO [11] SDA0 / SSPTXD / IOU Timer1 / GPIO [12] SCL1 / SCLK / IOU GPIO [13] KPROW[3] SDA1 / SSPRXD / IDU GPIO [14] / KPROW[2] UART0/UART1/UART2 TXD0 / IOU GPIO [5] RXD0 / IOU GPIO [6] TXD1 / IOU GPIO [7] RXD1 / IOU GPIO [8] CTS1/ TXD2(IrDA) / IOU PS2_CLK / GPIO [9] RTS1/ RXD2(IrDA) / IOU PS2_DATA / GPIO [10] SCHI/SDIO/XDMA SC0_DAT/ SD_CMD / IOU GPIO [29] / LCD_VD[17] SC0_CLK / SD_CLK / IO GPIO [28] / LCD_VD[16] I2C Serial Clock Line 0. USI Serial Frame. Timer0 time out output. General Purpose In/Out port [11]. I2C Serial Data Line 0 USI Serial Transmit Data Timer1 time out output General Purpose In/Out port [12] I2C Serial Clock Line 1 USI Serial Clock General Purpose In/Out port [13] Keypad row scan output [3] I2C Serial Data Line 1 USI Serial Receive Data General Purpose In/Out port [14] Keypad scan output [2] UART0 Transmit Data. General Purpose In/Out [5] UART0 Receive Data. General Purpose In/Out [6] UART1 Transmit Data. General Purpose In/Out [7] UART1 Receive Data. General Purpose In/Out [8] UART1 Clear To Send for Bluetooth application UART2 Transmit Data supporting SIR IrDA. PS2 Interface Clock Input/Output General Purpose In/Out [9] UART1 Request To Send for Bluetooth application UART2 Receive Data supporting SIR IrDA. PS2 Interface Bi-Directional Data Line. General Purpose In/Out [10] Smart Card I/O Contact to Card 0. SD/SDIO Mode - Command/Response; General Purpose In/Out [29] LCD data bus [17] Smart Card Clock Output to Card 0. SD/SDIO Mode - Clock; General Purpose In/Out [28] LCD data bus [16] - 23 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 5.1 W90P710 Pins Description (Continued) Pin Name SCHI/SDIO/XDMA SC0_RST / SD_DAT0 / GPIO [27] / LCD_VD[15] SC0_PRES / SD_DAT1 / GPIO [26] LCD_VD[14] SC0_nPWR / SD_DAT2 / GPIO [25] / LCD_VD[13] SC1_DAT / SD_DAT3 / GPIO [24] / LCD_VD[12] SC1_CLK / GPIO [23] / LCD_VD[11] SC1_RST / SD_CD / GPIO [22] / LCD_VD[10] SC1_PRES / nXDREQ / GPIO [21] / LCD_VD[9] SC1_nPWR / nXDACK / GPIO [20] / LCD_VD[8] Color LCD Interface IO Type Description Smart Card Reset Output to Card 0. SD/SDIO Mode - Data Line Bit 0; General Purpose In/Out [27] LCD data bus [15] Smart Card 0 Presence Contact Input. SD/SDIO Mode - Data Line Bit 1. General Purpose In/Out [26] LCD data bus [14] Smart Card 0 Power FET Control Signal Output. SD/SDIO Mode - Data Line Bit 2. General Purpose In/Out [25] LCD data bus [13] Smart Card I/O Contact to Card 1. SD/SDIO Mode - Data Line Bit 3; General Purpose In/Out [24] LCD data bus [12] Smart Card Clock Output to Card 1. General Purpose In/Out [23] LCD data bus [11] Smart Card Reset Output to Card 1. SD/SDIO Mode - Card Detect. General Purpose In/Out [22] LCD data bus [10] Smart Card 1 Presence Contact Input. External DMA Request. General Purpose In/Out [21] LCD data bus [9] Smart Card 1 Power FET Control Signal Output. External DMA Acknowledgement. General Purpose In/Out [20] LCD data bus [8] LCD Pixel Data Output. General Purpose In/Out [41:34] Horizontal Sync or Line Sync. General Purpose In/Out [33] Vertical Sync or Frame Sync. General Purpose In/Out [32] Data Enable or Display Control Signal. General Purpose In/Out [31] Pixel Clock. General Purpose In/Out [30] IO IO IO IO IO IO IO IO VD [7:0] / GPIO [41:34] HSYNC / GPIO [33] VSYNC / GPIO [32] VDEN / GPIO [31] VCLK / GPIO [30] IOU IOU IOU IOU IOU - 24 - W90P710 Table 5.1 W90P710 Pins Description (Continued) Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 P G P G P G P G P G Core Logic power (1.8V) Core Logic ground (0V) IO Buffer power (3.3V) IO Buffer ground (0V) USB power (3.3V) USB ground (0V) PLL Digital power (1.8V) PLL Digital ground (0V) PLL Analog power (1.8V) PLL Analog ground (0V) - 25 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List PIN NO. 1 2 3 4 5 6 7 8 9 DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 USB1.1 Host/Device Interface USB1VDD DP1 DN1 USB1VSS USB0VSS DN0 DP0 USB0VDD VDD33 USB1VDD DP1 DN1 USB1VSS USB0VSS DN0 DP0 USB0VDD VDD33 - UART[2:0]/PS2 Interface 10 11 12 13 14 15 16 GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] VSS33 GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] VSS33 UART_TXD0 UART_RXD0 UART_TXD1 UART_RXD1 UART_TXD2 UART_RXD2 I2C/USI Interface 17 18 19 20 21 22 GPIO[11] GPIO[12] GPIO[13] GPIO[14] VDD18 VSS18 GPIO[11] GPIO[12] GPIO[13] GPIO[14] VDD18 VSS18 I2C_SCL0 I2C_SDA0 I2C_SCL1 I2C_SDA1 SSP_FRAM SSP_TXD SSP_RXD SSP_SCLK TIMER0 TIMER1 KPI_ROW[3] KPI_ROW[2] UART_CTS1 UART_RTS1 PS2_CLK PS2_DATA - LCD /KeyPad Interface 23 24 25 26 27 GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[41] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[41] LCD_VCLK LCD_VDEN LCD_VSYNC LCD_HSYNC LCD_VD[7] KPI_ROW[0] KPI_ROW[1] KPI_ROW[2] KPI_ROW[3] KPI_COL[7] - - 26 - W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 LCD /KeyPad Interface 28 29 30 31 32 33 34 35 36 GPIO[40] GPIO[39] GPIO[38] GPIO[37] GPIO[36] GPIO[35] GPIO[34] VDD33 VSS33 GPIO[40] GPIO[39] GPIO[38] GPIO[37] GPIO[36] GPIO[35] GPIO[34] VDD33 VSS33 LCD_VD[6] LCD_VD[5] LCD_VD[4] LCD_VD[3] LCD_VD[2] LCD_VD[1] LCD_VD[0] KPI_COL[6] KPI_COL[5] KPI_COL[4] KPI_COL[3] KPI_COL[2] KPI_COL[1] KPI_COL[0] - System Reset & TEST 37 38 nRESET VSS33 nRESET VSS33 - PLL Power/Ground 39 40 41 42 PLL0_VDD18 PLL0_VSS18 PLL1_VDD18 PLL1_VSS18 PLL0_VDD18 PLL0_VSS18 PLL1_VDD18 PLL1_VSS18 - External IRQ[1:0]/USB Over Current 43 44 GPIO[16] GPIO[17] GPIO[16] GPIO[17] nIRQ[0] nIRQ[1] JTAG Interface 45 46 47 48 49 TMS TDI TDO TCK nTRST TMS TDI TDO TCK nTRST USB_OVRCUR - WatchDog/USB Power Enable 50 51 GPIO[15] VSS33 GPIO[15] VSS33 nWDOG USB_PWREN - - 27 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 System/RTC Clock 52 53 54 55 56 57 EXTAL(15M) XTAL(15M) VDD33 RTCVDD18 EXTAL(32K) XTAL(32K) EXTAL(15M) XTAL(15M) VDD33 RTCVDD18 EXTAL(32K) XTAL(32K) - AC97/I2S/PWM/UART3 Interface 58 59 60 61 62 63 64 GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] VDD18 VSS18 GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] VDD18 VSS18 AC97_nRESET AC97_DATAI AC97_DATAO AC97_SYNC AC97_BITCLK IRQ4 PWM0 PWM1 PWM2 PWM3 USB_PWREN UART_DTR3 UART_DSR3 UART_TXD3 UART_RXD3 - SmartCard/SDIO/USB Power/XDMAREQ/LCD Interace 65 66 67 68 69 70 71 72 73 74 75 76 GPIO[29] GPIO[28] GPIO[27] VDD33 GPIO[26] GPIO[25] GPIO[24] VSS33 GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[29] GPIO[28] GPIO[27] VDD33 GPIO[26] GPIO[25] GPIO[24] VSS33 GPIO[23] GPIO[22] GPIO[21] GPIO[20] SD_CMD SD_CLK SD_DAT[0] SD_DAT[1] SD_DAT[2] SD_DAT[3] USBPWREN SD_CD nXQREQ nXDACK SC0_IO SC0_CLK SC0_RST SC0_PRES SC0_PWR SC1_IO SC1_CLK SC1_RST SC1_PRES SC1_PWR LCD_VD[17] LCD_VD[16] LCD_VD[15] LCD_VD[14] LCD_VD[13] LCD_VD[12] LCD_VD[11] LCD_VD[10] LCD_VD[9] LCD_VD[8] - 28 - W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Ethernet RMII/KeyPad Interface 77 78 79 80 81 82 83 84 85 86 87 88 GPIO[42] GPIO[43] GPIO[44] VSS33 GPIO[45] GPIO[46] GPIO[47] GPIO[48] VDD33 GPIO[49] GPIO[50] GPIO[51] GPIO[42] GPIO[43] GPIO[44] VSS33 GPIO[45] GPIO[46] GPIO[47] GPIO[48] VDD33 GPIO[49] GPIO[50] GPIO[51] PHY_RXERR PHY_CRSDV PHY_RXD[0] PHY_RXD[1] PHY_REFCLK PHY_TXEN PHY_TXD[0] PHY_TXD[1] PHY_MDIO PHY_MDC KPI_COL[0] KPI_COL[1] KPI_COL[2] KPI_COL[3] KPI_COL[4] KPI_COL[5] KPI_COL[6] KPI_COL[7] KPI_ROW[0] KPI_ROW[1] LCD_VD[15] LCD_VD[16] LCD_VD[17] LCD_VD[8] LCD_VD[9] LCD_VD[10] LCD_VD[11] LCD_VD[12] LCD_VD[13] LCD_VD[14] Memory Address/Data/Control 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 A[0] A[1] A[2] A[3] A[4] VSS33 A[5] A[6] A[7] A[8] A[9] VDD33 A[10] A[11] A[12] A[13] A[0] A[1] A[2] A[3] A[4] VSS33 A[5] A[6] A[7] A[8] A[9] VDD33 A[10] A[11] A[12] A[13] - - 29 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 VSS18 A[14] A[15] A[16] VDD18 A[17] A[18] A[19] A[20] VSS33 A[21] D[31] D[30] D[29] D[28] VDD33 D[27] D[26] D[25] D[24] nECS[3] VSS33 VDD33 nECS[2] nECS[1] nECS[0] nOE nWAIT nBTCS MCKE VSS18 A[14] A[15] A[16] VDD18 A[17] A[18] A[19] A[20] VSS33 A[21] GPIO[67] GPIO[66] GPIO[65] GPIO[64] VDD33 GPIO[63] GPIO[62] GPIO[61] GPIO[60] nECS[3] VSS33 VDD33 nECS[2] nECS[1] nECS[0] nOE GPIO[71] nBTCS MCKE D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] nWAIT LCD_VD[23] LCD_VD[22] LCD_VD[21] LCD_VD[20] LCD_VD[19] LCD_VD[18] LCD_VD[17] LCD_VD[16] IRQ5 - - 30 - W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 152 153 154 155 156 157 158 159 160 161 162 nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nWE nWBE_SDQM[0] nWBE_SDQM[1] nWBE_SDQM[2] nWBE_SDQM[3] GPIO[18] GPIO[19] GPIO[59] D[22] D[21] D[20] D[20] D[19] D[18] D[17] D[16] VSS18 D[15] D[14] VDD18 D[13] D[12] nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nWE nWBE_SDQM[0] nWBE_SDQM[1] GPIO[69] GPIO[68] GPIO[18] GPIO[19] GPIO[59] GPIO[58] GPIO[57] GPIO[56] GPIO[56] GPIO[55] GPIO[54] GPIO[53] GPIO[52] VSS18 D[15] D[14] VDD18 D[13] D[12] nWBE_SDQM[2] nWBE_SDQM[3] nIRQ[2] nIRQ[3] D[23] D[22] D[21] D[20] D[20] D[19] D[18] D[17] D[16] LCD_VD[15] LCD_VD[14] LCD_VD[13] LCD_VD[12] LCD_VD[12] LCD_VD[11] LCD_VD[10] LCD_VD[9] LCD_VD[8] - - 31 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 163 164 165 166 167 168 169 170 171 172 173 174 175 176 D[11] D[10] VDD33 D[9] D[8] D[7] D[6] D[5] VSS33 D[4] D[3] D[2] D[1] D[0] D[11] D[10] VDD33 D[9] D[8] D[7] D[6] D[5] VSS33 D[4] D[3] D[2] D[1] D[0] - - 32 - W90P710 6. BLOCK DIAGRAM JTAG ICE TDMI Bus ARM7TDMI Wrapper PLL Clock Synthesizer Clock Synthesizer Cache Controller 4KB 4KB I-Cache D-Cache Real Time Clock *32768Hz 2 Timers 2 Smart Card Controllers (ISO-7816-3) * 15MHz PLL Power Management Unit AHB Bus APB Bus LCD Controller External Bus Interface RMII Bus Ethernet MAC Controller USB 1.1 Host Controller USB 1.1 Device Controller SDIO Host Controller Advanced Interrupt Controller Watch-Dog Timer AHB Arbiter PHY AHB Decoder I2C(x2)/USI UART (x4) with IrDA/Bluetooth/ Micro-printer 4-Channels PWM Timers 71 GPIOs PHY PHY * Host/Device APB Bridge 2-Channel GDMA W90P710 Block Diagram Keypad Controller PS/2 Keyboard Host Interface 2-channel AC97/I2S Fig 6.1 W90P710 Functional Block Diagram - 33 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7. FUNCTIONAL DESCRIPTION 7.1 ARM7TDMI CPU CORE The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. The high instruction throughput and impressive real-time interrupt response are the major benefits. The ARM7TDMI CPU core has two instruction sets: (1) The standard 32-bit ARM set (2) A 16-bit THUMB set The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM core while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers are used to speed up exception processing. All the register specified in ARM instructions can address any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt, memory aborts, attempted execution of an undefined instruction and software interrupts. A[31:0] Address Register Incrementer Bus Scan Control Address Incrementer Register Bank (31 x 32-bit registers) (6 status registers) B Bus PC Bus Instruction Decoder Control Logic 32 x8 Multiplier ALU Bus A Bus Barrel Shifter Instruction Pipeline Read Data Register Thumb Instruction Decoder Writer Data Register 32-bit ALU D[31:0] Fig 7.1 ARM7TDMI CPU Core Block Diagram - 34 - W90P710 7.2 7.2.1 System Manager Overview The W90P710 System Manager has the following functions. System memory map Data bus connection with external memory Product identifier register Bus arbitration PLL module Clock select and power saving control register Power-On setting 7.2.2 System Memory Map W90P710 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 - 0xFFFF_FFFF) and the OnChip RAM bank's start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable space: 0x0000_0000~0x7FDF_FFFF if Cache ON; non-cacheable space: 0x8000_0000~0xFFDF_FFFF). The size and location of each bank is determined by the register settings for "current bank base address pointer" and "current bank size". Please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You can use bank control registers to assign a specific bank start address by setting the bank's base pointer (13 bits). The address resolution is 256K bytes. The bank's start address is defined as "base pointer << 18" and the bank's size is "current bank size". In the event of an access requested to an address outside any programmed bank size, an abort signal is generated. The maximum accessible memory size of each external IO bank is 16M bytes (by word format), and 64M bytes on each SDRAM bank. - 35 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Cacheable space 0x7FFF_FFFF 512KB (Fixed) 0x7FF8.0000 512KB (Fixed) 0x7FF0_0000 Non-Cacheable space 0xFFFF_FFFF 512KB (Fixed) 0xFFF8_0000 512KB (Fixed) 0xFFF0_0000 RESERVED RESERVED RESERVED On-Chip APB Peripherals On-Chip AHB Peripherals RESERVED 8KB 0x7FE0_0000 RESERVED External I/O Bank 3 256KB - 16MB 8KB 0xFFE0_0000 On-Chip RAM 4KB,4KB External I/O Bank 3 256KB - 16MB External I/O Bank 2 256KB - 16MB External I/O Bank 2 256KB - 16MB External I/O Bank 1 256KB - 16MB EBI Space EBI Space External I/O Bank 1 256KB - 16MB External I/O Bank 0 256KB - 16MB External I/O Bank 0 256KB - 16MB SDRAM Bank 1 2MB - 64MB SDRAM Bank 1 2MB - 64MB SDRAM Bank 0 2MB - 64MB SDRAM Bank 0 2MB - 64MB ROM/FLASH 0x0000_0000 256KB - 16MB 0x8000_0000 ROM/FLASH 256KB - 32MB Fig7.2.1 System Memory Map - 36 - W90P710 Table 7.2.1 On-Chip Peripherals Memory Map BASE ADDRESS DESCRIPTION AHB Peripherals 0xFFF0_0000 0xFFF0_0004 0xFFF0_0008 0xFFF0_000C 0xFFF0_0010 0xFFF0_0014 0xFFF0_0020 0xFFF0_0024 0xFFF0_0028 0xFFF0_0030 0xFFF0_1000 0xFFF0_1004 0xFFF0_1008 0xFFF0_1018 0xFFF0_2000 0xFFF0_3000 0xFFF0_4000 0xFFF0_5000 0xFFF0_6000 0xFFF0_7000 0xFFF0_8000 0xFFF0_9000 0xFFF8_0000 0xFFF8_0100 0xFFF8_0200 0xFFF8_0300 0xFFF8_1000 0xFFF8_2000 0xFFF8_3000 0xFFF8_4000 0xFFF8_5000 0xFFF8_6000 0xFFF8_6100 0xFFF8_6200 Product Identifier Register (PDID) Arbitration Control Register (ARBCON) PLL Control Register 0(PLLCON0) Clock Select Register (CLKSEL) PLL Control Register 1 (PLLCON1) Audio IIS Clock Control Register (I2SCKCON) IRQ Wakeup Control Register (IRQWAKEUPCON) IRQ Wakeup Flag Register (IRQWAKEFLAG) Power Manager Control Register (PMCON) USB Transceiver Control Register (USBTXRCON) EBI Control Register (EBICON) Control Registers ROM/FLASH (ROMCON) Control Registers SDRAM bank 0 - 1 Control Registers External I/O 0 - 3 Control Registers Cache Controller Control Registers Ethernet MAC Controller Control Registers GDMA 0 - 1 Control Registers USB Host Controller Control Registers USB Device Controller Control Registers SDIO Host Controller Control Registers LCD Controller Control Registers AC97/I2S Controller Control Registers APB Peripherals UART 0 (Tx, RX for console) UART 1 (Tx, Rx, for blue-tooth) UART 2 (blue-tooth CTS, RTS/ IrDA Tx, Rx) UART 3 (micro-print DTR, DTS, Tx, Rx) Timer 0 - 1, WDOG Timer Interrupt Controller GPIO Real Time Clock Controller Control Registers (RTC) Smart Card Host Interface Control Registers (SCHI) I2C-0 Control Registers I2C-1 Control Registers USI Control Registers Publication Release Date: January 17, 2005 Revision A.2 - 37 - W90P710 Table 7.2.1 On-Chip Peripherals Memory Map (Continued) BASE ADDRESS DESCRIPTION APB Peripherals 0xFFF8_7000 0xFFF8_8000 0xFFF8_9000 Pulse Width Modulation (PWM) Control Registers KeyPad Interface Control Register (KPI) PS2 Control Registers 7.2.3 Address Bus Generation The W90P710 address bus generation is depended on the required data bus width of each memory bank. The data bus width is determined by DBWD bits in each bank's control register. The maximum accessible memory size of each external IO bank is 16M bytes. Table 7.2.2 Address Bus Generation Guidelines DATA BUS WIDTH EXTERNAL ADDRESS PINS A [21:0] MAXIMUM ACCESSIBLE MEMORY SIZE 8-bit 16-bit 32-bit A21 - A0 (Internal) A22 - A1 (Internal) A23 - A2 (Internal) 4M bytes 4M half-words 4M words 7.2.4 Data Bus Connection with External Memory 7.2.4.1. Memory formats The W90P710 can be configured as big endian or little endian mode by pull up or down the external data bus D14 pin. If D14 is pull-up then it is a little endian mode, otherwise, it is a big endian mode. Little endian In little endian format, the lowest addressed byte in a word is considered the least significant byte of the word and the highest addressed byte is the most significant. So the byte at address 0 of the memory system connects to data lines 7 through 0. For a word aligned address A, Fig7.2.2 shows how the word at address A, the half-word at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when D14 pin is High. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word at address A Half-word at address A+2 Byte at address A+3 Byte at address A+2 Half-word at address A Byte at address A+1 Byte at address A Fig7.2.2 Little endian addresses of bytes and half-words within words - 38 - W90P710 Big endian In Big endian format, the W90P710 stores the most significant byte of a word at the lowest numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects to data lines 31 through 24. For a word aligned address A, Fig7.2.3 shows how the word at address A, the half-word at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word at address A Half-word at address A Byte at address A Byte at address A+1 Half-word at address A+2 Byte at address A+2 Byte at address A+3 Fig7.2.3 Big endian addresses of bytes and half-words within words 7.2.4.2. Connection of External Memory with Various Data Width The system diagram for W90P710 connecting with the external memory is shown in Fig7.2.4. Below tables (Table7.2.3 through Table7.2.14) show the program/data path between CPU register and the external memory using little / big endian and word/half-word/byte access. W90P710 Fig7.2.4 Address/Data bus connection with external memory - 39 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Fig7.2.5 CPU registers Read/Write with external memory Table 7.2.3 and Table 7.2.4 Using big-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don't care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.3 Word access write operation with Big Endian ACCESS OPERATION XD WIDTH Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA nWBE [3-0] / SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence WORD 31 0 ABCD WA 31 0 ABCD 31 0 ABCD WA AAAA 31 0 ABCD 31 0 ABCD WRITE OPERATION (CPU REGISTER HALF WORD 31 0 ABCD WA 31 0 AB CD 15 0 AB WA XXAA 15 0 AB 15 0 AB 1st write 15 0 CD WA+2 XXAA 15 0 CD 15 0 CD 2nd write 70 A WA XXXA 70 A 70 A 1st write EXTERNAL MEMORY) BYTE 31 0 ABCD WA 31 0 ABCD 70 70 B C WA+1 XXXA 70 B 70 B 2nd write WA+2 XXXA 70 C 70 C 3rd write 70 D WA+3 XXXA 70 D 70 D 4th write - 40 - W90P710 Table7.2.4 Word access read operation with Big Endian ACCESS OPERATION XD WIDTH Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence WORD 31 0 ABCD WA 31 0 ABCD 31 0 ABCD WA AAAA 31 0 ABCD 31 0 ABCD READ OPERATION (CPU REGISTER HALF WORD 31 0 CDAB WA 31 0 CD AB 31 0 31 0 CD XX CD AB WA XXAA 15 0 CD 15 0 CD 1st read WA+2 XXAA 15 0 AB 15 0 AB 2nd read EXTERNAL MEMORY) BYTE 31 0 DCBA WA 31 0 DCBA 31 0 31 0 DCXX DCBX WA+1 XXXA 70 C 70 C 2nd read WA+2 XXXA 70 B 70 B 3rd read 31 0 DXXX WA XXXA 70 D 70 D 1st read 31 0 DCBA WA+3 XXXA 70 A 70 A 4th read Table 7.2.5 and Table 7.2.6 Using big-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0,2,4,6,8,A,C,E HAU = Address whose LSB is 2,6,A,E HAL = Address whose LSB is 0,4,8,C X = Don't care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.5 Half-word access write operation with Big Endian ACCESS OPERATION XD WIDTH Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA nWBE [3-0] / SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence HAL 31 0 CD CD 31 0 CD CD HAL AAUU 31 0 CD CD 31 16 CD WRITE OPERATION (CPU REGISTER WORD 31 0 ABCD HAU 31 0 CD CD 31 0 CD CD HAL UUAA 31 0 CD CD 15 0 CD HALF WORD 31 0 ABCD HA 31 0 CD CD 31 0 CD CD HA XXAA 15 0 CD 15 0 CD 31 0 CD CD 70 C HA XXXA 70 C 70 C 1st write EXTERNAL MEMORY) BYTE 31 0 ABCD HA 31 0 CD CD 70 D HA+1 XXXA 70 D 70 D 2nd write - 41 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table7.2.6 Half-word access read operation with Big Endian ACCESS OPERATION XD WIDTH Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence 15 0 AB HAL 15 0 AB 15 0 AB HAL AAUU 31 0 AB CD 31 0 ABCD READ OPERATION (CPU REGISTER WORD 15 0 CD HAU 15 0 CD 15 0 CD HAL UUAA 31 0 AB CD HALF WORD 15 0 CD HA 15 0 CD 15 0 CD HA XXAA 15 0 CD 15 0 CD EXTERNAL MEMORY) BYTE 15 0 DC HA 15 0 DC 15 0 DX HA XXXA 70 D 70 D 1st read 15 0 DC HA+1 XXXA 70 C 70 C 2nd read Table 7.2.7 and Table 7.2.8 Using big-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL = Address whose LSB is 0,2,4,6,8,A,C,E BA0 = Address whose LSB is 0,4,8,C BA2 = Address whose LSB is 2,6,A,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F BA1 = Address whose LSB is 1,5,9,D BA3 = Address whose LSB is 3,7,B,F - 42 - W90P710 Table7.2.7 Byte access write operation with Big Endian ACCESS OPERATION XD WIDTH Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA nWBE [3-0] / SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence BA0 31 0 DDDD 31 24 D BA0 AUUU 31 0 DXXX 31 24 D BA1 31 0 DDDD 23 16 D BA0 UAUU 31 0 XDXX 23 16 D WRITE OPERATION (CPU REGISTER WORD 31 0 ABCD BA2 31 0 DDDD 15 8 D BA0 UUAU 31 0 XXDX 15 8 D BA3 31 0 DDDD 70 D BA0 UUUA 31 0 XXXD 70 D BAL 31 0 DDDD 15 8 D BAL XXAU 15 0 DX 15 8 D EXTERNAL MEMORY) HALF WORD 31 0 ABCD BAU 31 0 DDDD 70 D BAL XXUA 15 0 XD 70 D BYTE 31 0 ABCD BA 31 0 DDDD 70 D BA XXXA 70 D 70 D Table7.2.8 Byte access read operation with Big Endian ACCESS OPERATION XD WIDTH Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence 70 A BA0 70 A 70 A BA0 AUUU 31 0 ABCD 70 B BA1 70 B 15 8 B BA0 UAUU 31 0 ABCD 31 0 ABCD READ OPERATION (CPU REGISTER WORD 70 C BA2 70 C 23 16 C BA0 UUAU 31 0 ABCD 70 D BA3 70 D 31 24 D BA0 UUUA 31 0 ABCD EXTERNAL MEMORY) HALF WORD 70 C BAL 70 C 70 C BAL XXAU 15 0 CD 15 0 CD 70 D BAU 70 D 15 8 D BAL XXUA 15 0 CD BYTE 70 D BA 70 D 70 D BA XXXA 70 D 70 D - 43 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 7.2.9 and Table 7.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don't care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.9 Word access write operation with little Endian Access Operation XD Width Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA nWBE [3-0] / SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence Word 31 0 ABCD WA 31 0 ABCD 31 0 ABCD WA AAAA 31 0 ABCD 31 0 ABCD Write Operation (CPU Register Half Word 31 0 ABCD WA 31 0 AB CD 15 0 CD WA XXAA 15 0 CD 15 0 CD 1st write 15 0 AB WA+2 XXAA 15 0 AB 15 0 AB 2nd write 70 D WA XXXA 70 D 70 D 1st write External Memory) Byte 31 0 ABCD WA 31 0 ABCD 70 70 C B WA+1 XXXA 70 C 70 C 2nd write WA+2 XXXA 70 B 70 B 3rd write 70 A WA+3 XXXA 70 A 70 A 4th write Table7.2.10 Word access read operation with Little Endian Access Operation XD Width Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence Word 31 0 ABCD WA 31 0 ABCD 31 0 ABCD WA AAAA 31 0 ABCD 31 0 ABCD Read Operation (CPU Register Half Word 31 0 ABCD WA 31 0 AB CD 31 0 31 0 XX CD AB CD WA XXAA 15 0 CD 15 0 CD 1st read WA+2 XXAA 15 0 AB 15 0 AB 2nd read External Memory) Byte 31 0 ABCD WA 31 0 ABCD 31 0 31 0 XXCD XBCD WA+1 XXXA 70 C 70 C 2nd read WA+2 XXXA 70 B 70 B 3rd read 31 0 XXXD WA XXXA 70 D 70 D 1st read 31 0 ABCD WA+3 XXXA 70 A 70 A 4th read - 44 - W90P710 Table 7.2.11 and Table 7.2.12 Using little-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0,2,4,6,8,A,C,E HAU = Address whose LSB is 2,6,A,E HAL = Address whose LSB is 0,4,8,C X = Don't care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.11 Half-word access write operation with little Endian Access Operation XD Width Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA nWBE [3-0] / SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence HAL 31 0 CD CD 31 0 CD CD HAL UUAA 31 0 CD CD 15 0 CD Write Operation (CPU Register Word 31 0 ABCD HAU 31 0 CD CD 31 0 CD CD HAL AAUU 31 0 CD CD 31 16 CD Half Word 31 0 ABCD HA 31 0 CD CD 31 0 CD CD HA XXAA 15 0 CD 15 0 CD 31 0 CD CD 70 D HA XXXA 70 D 70 D 1st write External Memory) Byte 31 0 ABCD HA 31 0 CD CD 70 C HA+1 XXXA 70 C 70 C 2nd write Table7.2.12 Half-word access read operation with Little Endian Access Operation XD Width Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence 15 0 CD HAL 15 0 CD 15 0 CD HAL UUAA 31 0 AB CD 31 0 ABCD Read Operation (CPU Register Word 15 0 AB HAU 15 0 AB 15 0 AB HAL AAUU 31 0 AB CD Half Word 15 0 CD HA 15 0 CD 15 0 CD HA XXAA 15 0 CD 15 0 CD External Memory) Byte 15 0 CD HA 15 0 CD 15 0 XD HA XXXA 70 D 70 D 1st read 15 0 CD HA+1 XXXA 70 C 70 C 2nd read - 45 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 7.2.13 and Table 7.2.14 Using little-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F Table7.2.13 Byte access write operation with little Endian Access Operation XD Width Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA nWBE [3-0] / SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence BA0 31 0 DDDD 70 D BA0 UUUA 31 0 XXXD 70 D BA1 31 0 DDDD 15 8 D BA0 UUAU 31 0 XXDX 15 8 D Write Operation (CPU Register Word 31 0 ABCD BA2 31 0 DDDD 23 16 D BA0 UAUU 31 0 XDXX 23 16 D BA3 31 0 DDDD 31 24 D BA0 AUUU 31 0 DXXX 31 24 D BAL 31 0 DDDD 70 D BAL XXUA 15 0 XD 70 D External Memory) Half Word 31 0 ABCD BAU 31 0 DDDD 15 8 D BAL XXAU 15 0 DX 15 8 D Byte 31 0 ABCD BA 31 0 DDDD 70 D BA XXXA 70 D 70 D Table7.2.14 Byte access read operation with Little Endian Access Operation XD Width Bit Number CPU Reg Data SA Bit Number SD Bit Number ED XA SDQM [3-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence 70 D BA0 70 D 70 D BA0 UUUA 31 0 ABCD 70 C BA1 70 C 70 C BA0 UUAU 31 0 ABCD 31 0 ABCD Read Operation (CPU Register Word 70 B BA2 70 B 70 B BA0 UAUU 31 0 ABCD 70 A BA3 70 A 70 A BA0 AUUU 31 0 ABCD External Memory) Half Word 70 D BAL 70 D 70 D BAL XXUA 15 0 CD 15 0 CD 70 C BAU 70 C 70 C BAL XXAU 15 0 CD Byte 70 D BA 70 D 70 D BA XXXA 70 D 70 D - 46 - W90P710 7.2.5 Bus Arbitration The W90P710's internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data transfers. Because the design of W90P710 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership. When bus mastership is granted to an internal function block or an external device, other pending requests are not acknowledged until the previous bus master has released the bus. W90P710 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode, depends on the ARBCON register PRTMOD bit setting. 7.2.5.1. Fixed Priority Mode In Fixed Priority Mode (PRTMOD=0, default value), to facilitate bus arbitration, priorities are assigned to each internal W90P710 function block. The bus controller arbitration requests for the bus mastership according to these fixed priorities. In the event of contention, mastership is granted to the function block with the highest assigned priority. These priorities are listed in Table 7.2.15. W90P710 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit 1 of the Arbitration Control Register (ARBCON), is set to "0", the priority of ARM Core is fixed to lowest. If IPEN bit is set to "1" and if no unmasked interrupt request, then the ARM Core's priority is still lowest and the IPACT=0, Bit 2 of the Arbitration Control Register (ARBCON) If there is an unmasked interrupt request, then the ARM Core's priority is raised to second and IPACT=1. If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in the interrupt handler. The IPACT bit can be read and written. Writing with "0", the IPACT bit is cleared, but it will be no effect as writing with "1". Table 7.2.15 Bus Priorities for Arbitration in Fixed Priority Mode BUS PRIORITY IPACT = 0 FUNCTION BLOCK IPEN = 1 AND IPACT = 1 1 (Highest) 2 3 4 5 6 7 8 9(Lowest) Audio Controller (AC97 & I2S) LCD General DMA0 General DMA1 EMC DMA SDIO USB Host USB Device ARM Core ARM Core Audio Controller (AC97 & I2S) LCD Controller General DMA0 General DMA1 EMC DMA SDIO USB Host USB Device - 47 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.2.5.2. Rotate Priority Mode In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored). W90P710 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain the bus and that a retracted master does not lock up the bus. 7.2.6 Power management W90P710 provide three power management scenarios to reduce power consumption. The peripherals' clocks can be enabled / disabled individually by controlling the co-responding bit in CLKSEL control register. Software can turn-off the unused modules' clocks to saving the unnecessary power consumption. It also provides idle and power-down modes to reduce power consumption. PD MIDLE EXTAL XTAL Crystal Oscillator 16-bit Counter HCLK_memc IDLE 480MHz PLL CLKS EnLCDclk HCLK EnEMCclk HCLK_cache HCLK_EMC HCLK_LCD ..... ..... W90P710 Clock Generator Fig. 7.2.6 W90P710 system clock generation diagram ..... IDLE MODE If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock to cache controller and ARM are stopped. W90P710 will exit idle state when nIRQ or nFIQ from any peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also be forced to enter idle state if both MIDLE and IDLE bits are set. Software must switch SDRAM into self-refresh mode before forcing memory to enter idle mode. - 48 - W90P710 IDLE Period FOUT (PLL) HCLK idle_state MCLK (ARM) HCLK (cache) HCLK (memc) Case1. IDLE=1, PD=0, MIDLE=0 Fig. 7.2.7 Clock management for system idle mode IDLE Period FOUT (PLL) HCLK idle_state MCLK (ARM) HCLK (cache) HCLK (memc) Case2. IDLE=1, PD=0, MIDLE=1 Fig. 7.2.8 Clock management for system and memory idle mode Power Down Mode This mode provides the minimum power consumption. When the W90P710 system is not working or waiting an external event, software can write PD bit "1" to turn off all the clocks includes system crystal oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode since the clock source is stopped. W90P710 will exit power down state when nIRQ/nFIQ is detected. W90P710 provides external interrupt nIRQ[3:0], keypad, and USB device interfaces to wakeup the system clock. - 49 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 65536 clocks EXTAL HCLK idle _state pd_state wake up by pheripheral's interrupts HCLK (cache) Case3. IDLE=0, PD=1, MIDLE=0 Fig 7.2.9 Clock management for system power down mode and wake up 7.2.7 Power-On Setting POWER-ON SETTING PIN After power on reset, there are eight Power-On setting pins to configure W90P710 system configuration. Internal System Clock Select Little/Big Endian Mode Select Boot ROM/FLASH Data Bus Width Default (Always pull-up in normal operation) D15 pinInternal System Clock Select If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock. If pin D15 is pull-up, the PLL output clock is used as internal system clock. D14 pinLittle/Big Endian Mode Select If pin D14 is pull-down, the external memory format is Big Endian mode. If pin D14 is pull-up, the external memory format is Little Endian mode. D [13:12] Boot ROM/FLASH Data Bus Width D [13:12] BUS WIDTH D15 D14 D [13:12] D [11:8] Pull-down Pull-down Pull-up Pull-up Pull-down Pull-up Pull-down Pull-up 8-bit 16-bit 32-bit RESERVED - 50 - W90P710 7.2.8 PDID ARBCON PLLCON0 CLKSEL PLLCON1 I2SCKCON System Manager Control Registers Map ADDRESS R/W DESCRIPTION RESET VALUE REGISTER 0xFFF0_0000 0xFFF0_0004 0xFFF0_0008 0xFFF0_000C 0xFFF0_0010 0xFFF0_0014 R R/W R/W R/W R/W R/W R/W R/W R/W R/W Product Identifier Register Arbitration Control Register PLL Control Register 0 Clock Select Register PLL Control Register 1 Audio IIS Clock Control Register IRQ Wakeup Control register IRQ wakeup Flag Register Power Manager Control Register USB Transceiver Control Register 0xX090_0710 0x0000_0000 0x0000_2F01 0x1FFF_3FX8 0x0001_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 IRQWAKECON 0xFFF0_0020 IRQWAKEFLAG 0xFFFF_0024 PMCON USBTxrCON 0xFFF0_0028 0xFFF0_0030 Product Identifier Register PDID This register is read only and lets software can use it to recognize certain characteristics of the chip ID and the version number. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PDID 31 23 15 7 0xFFF0_0000 30 22 14 6 29 21 13 5 R Product Identifier Register 28 20 12 4 CHPID 27 19 CHPID 11 CHPID 3 2 1 10 9 26 VERSION 18 17 25 0xX090_0710 24 16 8 0 PACKAGE - 51 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION Package Type Select [31:30] PACKAGE These two bits are power-on setting latched from pin D[9:8] Package [31:30] 1 1 Version of chip The chip identifier 0x090.0710 Package Type 176-pin Package [29:24] [23:0] VERSION CHIPID Arbitration Control Register (ARBCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ARBCON 0xFFF0_0004 30 22 14 6 29 21 13 5 R/W Arbitration Control Register 0x0000_0000 25 17 9 1 IPEN 24 16 8 0 PRTMOD 31 23 15 7 28 20 12 4 27 19 11 3 26 18 10 2 IPACT RESERVED RESERVED RESERVED RESERVED BITS DESCRIPTION [31:3] [2] RESERVED IPACT [1] IPEN [0] PRTMOD Interrupt priority active. When IPEN="1", this bit will be set when the ARM core has an unmasked interrupt request. This bit is available only when the PRTMOD=0. Interrupt priority enable bit 0 = the ARM core has the lowest priority. 1 = enable to raise the ARM core priority to second This bit is available only when the PRTMOD=0. Priority mode select 0 = Fixed Priority Mode (default) 1 = Rotate Priority Mode - 52 - W90P710 PLL Control Register0 PLLCON0 W90P710 provides two clock generation options - crystal and oscillator. The external clock via EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL's output clock for the internal system clock, D15 pin must be pull-up. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PLLCON 0xFFF0_0008 30 29 R/W 28 PLL Control Register 0x0000_2F01 25 24 31 27 26 RESERVED 23 22 21 20 RESERVED 15 14 13 12 FBDV 7 FBDV 6 OTDV 5 4 3 2 INDV 1 0 11 10 9 19 18 17 16 PWDEN 8 BITS DESCRIPTION [31:17] [16] RESERVED PWDEN Power down mode enable 0 = PLL is in normal mode (default) 1 = PLL is in power down mode PLL VCO output clock feedback divider Feedback Divider divides the output clock from VCO of PLL. PLL output clock divider OTDV [6:5] DIVIDED BY [15:7] FBDV [6:5] OTDV 0 0 1 1 0 1 0 1 1 2 2 4 [4:0] INDV PLL input clock divider Input divider divides the input reference clock into the PLL. - 53 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 EXTAL FIN USBCKS GP0 INDV[4:0] Input Divider (NR) PLL Charge Pump VCO Output 480MHz Divider FOUT (NO) 48MHz Gen 1 0 USB Module PFD FBDV[8:0] Feedback Divider (NF) Clock Divider & Selector 0 1 Internal System Clock ECLKS OTDV[1:0] CLKS[2:0] Fig 7.2.8.1 System PLL block diagram The formula of output clock of PLL is: FOUT = FIN NF 1 NR NO FOUTOutput clock of Output Divider FINExternal clock into the Input Divider NRInput divider value (NR = INDV + 2) NFFeedback divider value (NF = FBDV + 2) NOOutput divider value (NO = OTDV) Clock Select Register (CLKSEL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CLKSEL 0xFFF0_000C 30 RESERVED 22 UART2 14 USBD 6 TIMER 29 21 UART1 13 GDMA 5 UART R/W 28 PS2 20 Clock Select Register 0x1FFF_7FX8 26 25 SCH0 17 PWM 9 RESERVED 1 24 SSP 16 AC97 8 WDT 0 RESET 31 23 UART3 15 USBCKS 7 USBH 27 KPI 19 I2C0 11 LCD 3 SCH1 18 RTC 10 EMC 2 CLKS I2C1 12 SDIO 4 ECLKS - 54 - W90P710 BITS DESCRIPTION [31:29] [28] RESERVED PS2 PS2 controller clock enable bit 0 = Disable PS2 controller clock 1 = Enable PS2 controller clock Keypad controller clock enable bit [27] KPI 0 = Disable keypad controller clock 1 = Enable keypad controller clock Smart Card Host controller 1 clock enable bit [26] SCH1 0 = Disable smart card host controller 1 clock 1 = Enable smart card host controller 1 clock Smart Card Host controller 0 clock enable bit [25] SCH0 0 = Disable smart card host controller 0 clock 1 = Enable smart card host controller 0 clock USI controller clock enable bit [24] USI 0 = Disable USI controller clock 1 = Enable USI controller clock UART3 controller clock enable bit [23] UART3 0 = Disable UART3 controller clock 1 = Enable UART3 controller clock UART2 controller clock enable bit [22] UART2 0 = Disable UART2 controller clock 1 = Enable UART2 controller clock UART1 controller clock enable bit [21] UART1 0 = Disable UART1 controller clock 1 = Enable UART1 controller clock I2C1 controller clock enable bit [20] I2C1 0 = Disable I2C1 controller clock 1 = Enable I2C1 controller clock I2C0 controller clock enable bit [19] I2C0 0 = Disable I2C0 controller clock 1 = Enable I2C0 controller clock RTC unit clock enable bit [18] RTC 0 = Disable RTC controller clock 1 = Enable RTC controller clock - 55 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION PWM controller clock enable bit [17] PWM 0 = Disable PWM controller clock 1 = Enable PWM controller clock Audio Controller clock enable bit [16] AC97 0 = Disable AC97 controller clock 1 = Enable AC97 controller clock USB host/device 48MHz clock source Select bit [15] USBCKS 0 = USB clock 48MHz input from internal PLL (480MHz/10) 1 = USB clock 48MHz input from external GPIO0 pin, this pin direction must set to input. USB device clock enable bit [14] USBD 0 = Disable USB device controller clock 1 = Enable USB device controller clock GDMA controller clock enable bit [13] GDMA 0 = Disable GDMA clock 1 = Enable GDMA clock SD/SDIO host controller clock enable bit [12] SDIO 0 = Disable SDIO controller clock 1 = Enable SDIO controller clock LCD controller clock enable bit [11] LCD 0 = Disable LCD controller clock 1 = Enable LCD controller clock EMC controller clock enable bit [10] [9] [8] EMC RESERVED WDT 0 = Disable EMC controller clock 1 = Enable EMC controller clock WDT clock enable bit 0 = Disable WDT counting clock 1 = Enable WDT counting clock USB host clock enable bit [7] USBH 0 = Disable USB host controller clock 1 = Enable USB host controller clock Timer clock enable bit [6] TIMER 0 = Disable timer clock 1 = Enable timer clock - 56 - W90P710 Continued. BITS DESCRIPTION UART0 controller clock enable bit [5] UART0 0 = Disable UART0 controller clock 1 = Enable UART0 controller clock External clock select 0 = External clock from EXTAL pin is used as system clock [4] ECLKS 1 = PLL output clock is used as system clock After power on reset, the content of ECLKS is the Power-On Setting value. You can program this bit to change the system clock source. PLL output clock select CLKS [3:1] 0 0 0 0 1 [3:1] CLKS 1 1 1 Note: 1. This values are based on PLL output(FOUT) is 480MHz. 2. When 24Mhz ~ 80MHz is selected, the ECLKS bit must be set to 1. 3. About 58.594KHz setting, two steps are needed. First, clear ECLKS bit, and then clear CLKS. Software Reset bit [0] RESET This is a software reset control bit. Set logic 1 to generate an internal reset pulse. This bit is auto-clear to logic 0 at the end of the reset pulse. 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 System clock 58.594 KHz* 24 MHz 48 MHz 60 MHz 80 MHz RESERVED RESERVED RESERVED - 57 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 PLL Control Register 1PLLCON1 W90P710 provides extra PLL for LCD controller programmable pixel clock and provide 12.288/16.934 MHz clock source to Audio Controller. It uses the same 15MHz crystal clock input source with system PLL mentioned above. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PLLCON1 31 0xFFF0_0010 30 29 R/W PLL Control Register 1 28 27 26 25 0x0001_0000 24 RESERVED 23 22 21 20 RESERVED 15 14 13 12 FBDV1 7 FBDV1 BITS 19 18 17 16 PWDEN1 11 10 9 8 6 OTDV1 5 4 3 2 INDV1 1 0 DESCRIPTION [31:17] [16] [15:7] RESERVED PWDEN1 FBDV1 PLL1 power down enable 0 = PLL1 is in normal mode 1 = PLL1 is in power down mode (default) PLL1 VCO output clock feedback divider Feedback Divider divides the output clock from VCO of PLL1. PLL1 output clock divider OTDV1 [6:5] Divided by 0 0 1 0 1 2 1 0 2 1 1 4 PLL1 input clock divider Input divider divides the input reference clock into the PLL1. [6:5] OTDV1 [4:0] INDV1 - 58 - W90P710 EXTAL FIN INDV1[4:0] Input Divider (NR) PLL1 Charge Pump VCO Output 480MHz Divider FOUT (NO) to LCD controller PFD FBDV1[8:0] Feedback Divider (NF) to Audio Controller OTDV1[1:0] Fig 7.2.8.2 LCD PLL block diagram The formula of output clock of PLL is: FOUT = FIN NF 1 NR NO FOUTOutput clock of Output Divider FINExternal clock into the Input Divider NRInput divider value (NR = INDV1 + 2) NFFeedback divider value (NF = FBDV1 + 2) NOOutput divider value (NO = OTDV1) - 59 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 IIS Clock Control Register (I2SCKCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2SCKCON 0xFFF0_0014 31 23 15 7 30 22 14 6 29 21 13 5 R/W I2S PLL clock Control Register 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 IISPLLEN 0 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 PRESCALE DESCRIPTION BITS [31:9] RESERVED IIS PLL clock source enable Set this bit will enable PLL1 clock output to audio I2S clock input. 1 = Enable PLL1 clock source for audio I2S 0 = Disable PLL1 clock source for audio I2S The PLL1 is shared with LCD controller, if both the LCD and I2S are used the PLL at the same time, software can using this prescaler to generate an appropriate clock nearly 12.288M or 16.934M. The clock is generated as below, and if PRESCALE =0, the PLL_AUDIO is the same frequency as FOUT "PLL_AUDIO = PLL_FOUT/(PRESCALE +1)" [8] I2SPLLEN [7:0] PRESCALE IRQ Wakeup Control Register (IRQWAKECON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE IRQWAKECON 31 23 15 7 0xFFF0_0020 30 22 14 29 21 13 R/W IRQ Wakeup Control Register 27 19 11 3 26 18 10 25 17 9 0x0000_0000 24 16 8 0 6 5 IRQWAKEUPPOL 28 RESERVED 20 RESERVED 12 RESERVED 4 2 1 IRQWAKEUPEN - 60 - W90P710 BITS DESCRIPTION [31:8] [7] RESERVED nIRQ3 wake up polarity IRQWAKEUPPOL[3] 1 = nIRQ3 is high level wake up 0 = nIRQ3 is low level wake up nIRQ2 wake up polarity [6] IRQWAKEUPPOL[2] 1 = nIRQ2 is high level wake up 0 = nIRQ2 is low level wake up nIRQ1 wake up polarity [5] IRQWAKEUPPOL[1] 1 = nIRQ1 is high level wake up 0 = nIRQ1 is low level wake up nIRQ0 wake up polarity [4] IRQWAKEUPPOL[0] 1 = nIRQ0 is high level wake up 0 = nIRQ0 is low level wake up nIRQ3 wake up enable bit [3] IRQWAKEUPEN[3] 1 = nIRQ3 wake up enable 0 = nIRQ3 wake up disable nIRQ2 wake up enable bit [2] IRQWAKEUPEN[2] 1 = nIRQ2 wake up enable 0 = nIRQ2 wake up disable nIRQ1 wake up enable bit [1] IRQWAKEUPEN[1] 1 = nIRQ1 wake up enable 0 = nIRQ1 wake up disable nIRQ0 wake up enable bit [0] IRQWAKEUPEN[0] 1 = nIRQ0 wake up enable 0 = nIRQ0 wake up disable IRQ Wakeup Flag Register (IRQWAKEFLAG) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE IRQWAKEFLAG 0xFFF0_0024 R/W IRQ Wakeup Flag Register 0x0000_0000 - 61 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 29 21 13 6 5 RESERVED 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 26 18 10 25 17 9 24 16 8 0 2 1 IRQWAKEFLAG This register is used to record the wakeup event, after clock recovery, software should check these flags to identify which nIRQ is used to wakeup the system. And clear the flags in IRQ interrupt sevice routine. BITS DESCRIPTION [31:4] [3] RESERVED IRQWAKEFLAG[ 3] IRQWAKEFLAG[ 2] IRQWAKEFLAG[ 1] IRQWAKEFLAG[ 0] nIRQ3 wake up flag 1 = chip is waked up by nIRQ3 0 = no active nIRQ2 wake up flag 1 = chip is waked up by nIRQ2 0 = no active nIRQ1 wake up flag 1 = chip is waked up by nIRQ1 0 = no active nIRQ0 wake up flag 1 = chip is waked up by nIRQ0 0 = no active [2] [1] [0] Power Management Control Register (PMCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PMCON 31 23 15 7 0xFFF0_0028 30 22 14 6 29 21 13 R/W Power Management Control Register 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 26 18 10 2 MIDLE 25 17 9 1 PD 0x0000_0000 24 16 8 0 IDLE 5 RESERVED - 62 - W90P710 BITS DESCRIPTION [31:3] RESERVED Memory controller IDLE enable Setting both MIDLE and IDLE bits HIGH will let memory controller enter IDLE mode, the clock source of memory controller will be halted while ARM CORE enter IDLE mode. [2] MIDLE 1=memory controller will be forced into IDLE mode, (clock of memory controller will be halted), when IDLE bit is set. 0 = memory controller still active when IDLE bit is set. NOTE: Software must let SDRAM enter self-refresh mode before enable this function because SDRAM MCLK will be stopped. Power down enable Setting this bit HIGH will let W90P710 enter power saving mode. The clock source 15M crystal oscillator and PLLs are stopped to generate clock. User can use nIRQ[3:0], keypad and external RESET to wakeup W90P710. 1 = Enable power down 0 = Disable IDLE mode enable Setting this bit HIGH will let ARM Core enter power saving mode. The peripherals can still keep working if the clock enable bit in CLKSEL is set. Any nIRQ or nFIQ to ARM Core will let ARM CORE to exit IDLE state. 1 = IDLE mode 0 = Disable [1] PD [0] IDLE USB Transceiver Control Register (USBTXRCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USBTXRCO N 31 23 15 7 0xFFF0_0030 30 22 14 6 29 21 13 5 R/W USB Transceiver Control Register 0x0000_0000 24 16 8 0 USBHnD 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 RESERVED 26 18 10 2 25 17 9 1 - 63 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:1] RESERVED USBHnD[0]: USB transceiver control [0] USBHnD There are two USB1.1 built-in transceivers for data transmission. One is dedicated for USB host and the other is shared with USB device. Software can program this bit to switch the transceiver path. 1 = HOST 0 = Device - 64 - W90P710 7.3 7.3.1 External Bus Interface EBI Overview W90P710 supports External Bus Interface (EBI), which controls the access to the external memory (ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 22 bits. It supports 8-bit, 16-bit, and 32-bit external data bus width for each bank. The EBI has the following functions SDRAM controller EBI control register ROM/FLASH interface External I/O interface External bus mastership 7.3.2 SDRAM Controller The SDRAM controller module within W90P710 contains configuration registers timing control registerscommon control register and other logic to provide 81632 bits SDRAM interface with a single 81632 bits SDRAM device or two 8-bit devices wired to give a 16-bit data path or two 16-bit devices wired to give a 32-bit data path. The maximum size of each bank is 64M bytes, and maximum memory size can span up to 128MB. The SDRAM controller has the following features Supports up to 2 external SDRAM banks Maximum size of each bank is 64M bytes 81632-bit data interface Programmable CAS Latency 12 and 3 Fixed Burst Length 1 Sequential burst type Auto Refresh Mode and Self Refresh Mode Adjustable Refresh Rate Power up sequence - 65 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.3.2.1. SDRAM Components Supported Table 7.3.2.1 SDRAM supported by W90P710 SIZE TYPE BANKS ROW ADDRESSING COLUMN ADDRESSING 16M bits 64M bits 128M bits 256M bits 2Mx8 1Mx16 8Mx8 4Mx16 2Mx32 16Mx8 8Mx16 4Mx32 32Mx8 16Mx16 2 2 4 4 4 4 4 4 4 4 RA0~RA10 RA0~RA10 RA0~RA11 RA0~RA11 RA0~RA10 RA0~RA11 RA0~RA11 RA0~RA11 RA0~RA12 RA0~RA12 CA0~CA8 CA0~CA7 CA0~CA8 CA0~CA7 CA0~CA7 CA0~CA9 CA0~CA8 CA0~CA7 CA0~CA9 CA0~CA8 AHB Bus Address Mapping to SDRAM Bus Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used; The HADDR prefixes have been omitted on the following tables. A14 ~ A0 are the Address pins of the W90P710 EBI interface; A14 and A13 are the Bank Select Signals of SDRAM. SDRAM Data Bus Width: 32-bit Total 16M Type 2Mx8 RxC 11x9 R/C R C 16M 1Mx16 11x8 R C 64M 8Mx8 12x9 R C 64M 4Mx16 12x8 R C 64M 2Mx32 11x8 R C 128M* 16Mx8 12x10 R C 128M 8Mx16 12x9 R C 128M 4Mx32 12x8 R C 256M* 32Mx8 13x10 R C 256M* 16Mx16 13x9 R C A14 (BS1) ** ** ** ** 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 A13 (BS0) 11 11 10 10 12 12 10 10 10 10 12 12 12 12 10 10 12 12 12 12 A12 ** ** ** ** 11* 11* 11* 11* 11* 11* 11* 11* 11* 11* 11* 11* 24 24* 24 24* A11 11* 11* 10* 10* 23 23* 23 23* 23* 23* 23 23* 23 23* 23 23* 23 23* 23 23* A10 22 AP 11 AP 22 AP 22 AP 22 AP 22 AP 22 AP 22 AP 22 AP 22 AP A9 21 25* 21 25* 21 25* 21 25* 21 25* 21 25 21 25* 21 25* 21 26* 21 26* A8 20 10 20 10* 20 10 20 24* 20 24* 20 10 20 10 20 10* 20 10 20 10* A7 19 9 19 9 19 9 19 9 19 9 19 9 19 9 19 9 19 9 19 9 A6 18 8 18 8 18 8 18 8 18 8 18 8 18 8 18 8 18 8 18 8 A5 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 A4 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 A3 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 A2 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 A1 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 A0 12 2 12 2 24 2 12 2 12 2 24 2 24 2 12 2 25 2 25 2 - 66 - W90P710 SDRAM Data Bus Width: 16-bit Total 16M Type 2Mx8 RxC 11x9 R/C R C 16M 1Mx16 11x8 R C 64M 8Mx8 12x9 R C 64M 4Mx16 12x8 R C 64M 2Mx32 11x8 R C 128M 16Mx8 12x10 R C 128M 8Mx16 12x9 R C 128M 4Mx32 12x8 R C 256M* 32Mx8 13x10 R C 256M 16Mx16 13x9 R C A14 (BS1) ** ** ** ** 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 A13 (BS0) 10 10 9 9 11 11 9 9 9 9 11 11 11 11 9 9 11 11 11 11 A12 ** ** ** ** 10* 10* 10* 10* 10* 10* 10* 10* 10* 10* 10* 10* 23 23* 23 23* A11 10* 10* 9* 9* 22 22* 22 22* 22* 22* 22 22* 22 22* 22 22* 22 22* 22 22* A10 21 AP 10 AP 21 AP 21 AP 21 AP 21 AP 21 AP 21 AP 21 AP 21 AP A9 20 24* 20 24* 20 24* 20 24* 20 24* 20 24 20 24* 20 24* 20 25* 20 25* A8 19 9 19 9* 19 9 19 23* 19 23* 19 9 19 9 19 9* 19 9 19 9 A7 18 8 18 8 18 8 18 8 18 8 18 8 18 8 18 8 18 8 18 8 A6 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 A5 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 A4 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 A3 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 A2 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 A1 12 2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 A0 11 1 11 1 23 1 11 1 11 1 23 1 23 1 11 1 24 1 24 1 - 67 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 SDRAM Data Bus Width: 8-bit Total 16M Type 2Mx8 RxC 11x9 R/C R C 16M 1Mx16 11x8 R C 64M 8Mx8 12x9 R C 64M 4Mx16 12x8 R C 64M 2Mx32 11x8 R C 128M 16Mx8 12x10 R C 128M 8Mx16 12x9 R C 128M 4Mx32 12x8 R C 256M 32Mx8 13x10 R C 256M 16Mx16 13x9 R C A14 A13 (BS1) (BS0) ** ** ** ** 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 8 8 10 10 8 8 8 8 10 10 10 10 8 8 10 10 10 10 A12 ** ** ** ** 9* 9* 9* 9* 9* 9* 9* 9* 9* 9* 9* 9* 22 22* 22 22* A11 9* 9* 8* 8* 21 21* 21 21* 21* 21* 21 21* 21 21* 21 21* 21 21* 21 21* A10 20 AP 9 AP 20 AP 20 AP 20 AP 20 AP 20 AP 20 AP 20 AP 20 AP A9 19 23* 19 23* 19 23* 19 23* 19 23* 19 23 19 23* 19 23* 19 24 19 24* A8 18 8 18 8* 18 8 18 22* 18 22* 18 8 18 8 18 8* 18 8 18 8 A7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 17 7 A6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 16 6 A5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 15 5 A4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 14 4 A3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 13 3 A2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 12 2 A1 11 1 11 1 11 1 11 1 11 1 11 1 11 1 11 1 11 1 11 1 A0 10 0 10 0 22 1 10 0 10 0 22 0 22 0 10 0 23 0 23 0 7.3.2.2. SDRAM Power Up Sequence The SDRAM must be initialized predefined manner after power on.W90P710 SDRAM Controller automatically executes the commands needed for initialion and set the mode register of each bank to default value. The default value is -- Burst Length = 1 -- Burst Type = Sequential (fixed) -- CAS Latency = 2 -- Write Burst Length = Burst (fixed) The value of mode register can be changed after power up sequence by setting the value of corresponding bank's configuration register "LENGTH" and "LATENCY" bits and set the MRSET bit enable to execute the Mode Register Set command. - 68 - W90P710 7.3.2.3. SDRAM Interface A [ 2 1 :0 ] A [ 1 0 :0 ] A13 A14 D [ 3 1 :0 ] M CLK M CKE n S C S [ 1 :0 ] nSRAS nSCAS nSW E n S D Q M [ 3 :0 ] n S D Q M [ 3 :0 ] nSCS0 A [ 1 0 :0 ] BS0 BS1 D Q [ [ 3 1 :0 ] CLK CKE nCS nRAS nCAS nW E D Q M [ 3 :0 ] W 90P710 Fig 7.3.1 SDRAM Interface SDRAM 64M b 512Kx4x32 7.3.3 EBI Control Registers Map ADDRESS R/W DESCRIPTION RESET VALUE REGISTER EBICON ROMCON SDCONF0 SDCONF1 SDTIME0 SDTIME1 EXT0CON EXT1CON EXT2CON EXT3CON CKSKEW 0xFFF0_1000 0xFFF0_1004 0xFFF0_1008 0xFFF0_100C 0xFFF0_1010 0xFFF0_1014 0xFFF0_1018 0xFFF0_101C 0xFFF0_1020 0xFFF0_1024 0xFFF0_1F00 R/W EBI control register R/W ROM/FLASH control register R/W SDRAM bank 0 configuration register R/W SDRAM bank 1 configuration register R/W SDRAM bank 0 timing control register R/W SDRAM bank 1 timing control register R/W External I/O 0 control register R/W External I/O 1 control register R/W External I/O 2 control register R/W External I/O 3 control register R/W Clock skew control register (for testing) 0x0001_0000 0x0000_0XFC 0x0000_0800 0x0000_0800 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_0038 - 69 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 EBI Control Register (EBICON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EBICON 0xFFF0_1000 R/W EBI control register 0x0001_0000 31 30 29 28 27 EXBE3 26 EXBE2 18 REFEN 25 EXBE1 17 REFMOD 9 24 EXBE0 16 CLKEN 8 RESERVED 23 22 21 RESERVED 15 14 13 12 20 19 11 REFRAT 10 7 6 5 REFRAT 4 3 2 WAITVT 1 0 LITTLE BITS DESCRIPTION [31:28] RESERVED External IO bank 3 byte enable This function is used for some devices that with high and low bytes enable signals to control which byte will be write or mask data output when read. For this kind device, software can set this bit HIGH to implement this function. Detail pin interconnection is showed as Fig7.3.8. 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM. 0 = nWBE[3:0] pin is byte write strobe signal. External IO bank 2 byte enable The bit function description is the same as EXBE3 above. [27] EXBE3 [26] EXBE2 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM. 0 = nWBE[3:0] pin is byte write strobe signal. External IO bank 1 byte enable The bit function description is the same as EXBE3 above. [25] EXBE1 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM 0 = nWBE[3:0] pin is byte write strobe signal - 70 - W90P710 Continued. BITS DESCRIPTION External IO bank 0 byte enable This bit function description is the same as EXBE3 above. [24] EXBE0 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM 0 = nWBE[3:0] pin is byte write strobe signal [23:19] RESERVED Enable SDRAM refresh cycle for SDRAM bank0 & bank1 [18] REFEN This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is according to REFRAT bits. 1 = enable refresh function 0 = disable refresh function Refresh mode of SDRAM for SDRAM bank Defines the refresh mode type of external SDRAM bank Software can write this bit "1" to force SDRAM enter self-refresh mode. [17] REFMOD 0 = Auto refresh mode 1 = Self refresh mode NOTE: If any read/write to SDRAM occurs then this bit will be cleared to "0" by hardware automatically and SDRAM will enters auto-refresh mode. Clock enable for SDRAM [16] CLKEN Enables the SDRAM clock enable (CKE) control signal 0 = Disable (power down mode) 1 = Enable Default Refresh count value for SDRAM The SDRAM Controller automatically provides an auto refresh cycle for every refresh period programmed into the REFRAT bits when the REFEN bit of each bank is set The refresh period is calculated as period = [15:3] REFRAT value fMCLK - 71 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION Valid time of nWAIT signal W90P710 recognizes the nWAIT signal at the next "nth" MCLK rising edge after the nOE or nWBE active cycle. WAITVT bits determine the n. [2:1] WAITVT WAITVT [2:1] 0 0 1 1 Little Endian mode After power on reset, the content of LITTLE is the Power-On Setting value from D14 pin. If pin D14 is pull-down, the external memory format is Big Endian mode. If pin D14 is pull-up, the external memory format is Little Endian mode. For more detail, refer to Power-On Setting of System Manager. NOTE: This bit is read only. 0 1 0 1 nth MCLK 1 2 3 4 [0] LITTLE ROM/Flash Control Register ROMCON REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ROMCON 0xFFF0_1004 R/W ROM/FLASH control register 0x0000_0XFC 31 30 29 28 27 26 25 24 BASADDR 23 22 21 BASADDR 15 14 13 12 11 10 tPA 4 3 BTSIZE 2 1 PGMODE 0 20 19 18 17 SIZE 9 8 16 RESERVED 7 6 tACC 5 - 72 - W90P710 BITS DESCRIPTION [31:19] BASADDR Base address pointer of ROM/Flash bank The start address is calculated as ROM/Flash bank base pointer << 18. The base address pointer together with the "SIZE" bits constitutes the whole address range of each bank. The size of ROM/FLASH memory SIZE [10:8] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Page mode access cycle time tPA[11:8] MCLK 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 Byte 256K 512K 1M 2M 4M 8M 16M RESERVED [18:16] SIZE [15:12] RESERVED [11:8] tPA 1 1 1 1 1 1 1 1 tPA[11:8] 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 MCLK 10 12 14 16 18 20 22 24 [7:4] tACC Access cycle time tACC[11:8] 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 MCLK 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 tACC[11:8] 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 MCLK 10 12 14 16 18 20 22 24 - 73 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION Boot ROM/FLASH data bus width This ROM/Flash bank is designed for a boot ROM. BASADDR bits determine its start address. The external data bus width is determined by the data bus signals D [13:12] power-on setting. [3:2] BTSIZE BTSIZE [3:2] 0 0 0 1 1 0 1 1 Bus Width 8-bit 16-bit 32-bit RESERVED D [13:12] Bus Width Pull-down Pull-down 8-bit Pull-down Pull-up 16-bit Pull-up Pull-down 32-bit Pull-up Pull-up RESERVED Page mode configuration PGMODE [1:0] [1:0] PGMODE 0 0 1 1 0 1 0 1 Mode Normal ROM 4 word page 8 word page 16 word page Fig7.3.2 ROM/FLASH Read Operation Timing - 74 - W90P710 Fig 7.3.3 ROM/FLASH Page Read Operation Timing Configuration RegistersSDCONF0/1 The configuration registers enable software to set a number of operating parameters for the SDRAM controller. There are two configuration registers SDCONF0SDCONF1 for SDRAM bank 0bank 1 respectively. Each bank can have a different configuration. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SDCONF0 SDCONF1 0xFFF0_1008 0xFFF0_100C R/W SDRAM bank 0 configuration register R/W SDRAM bank 1 configuration register 0x0000_0800 0x0000_0800 31 30 29 28 BASADDR 27 26 25 24 23 22 21 BASADDR 20 19 18 17 RESERVED 16 15 MRSET 7 COMPBK 14 RESERVED 13 AUTOPR 5 DBWD 12 LATENCY 4 COLUMN 11 10 9 RESERVED 8 6 3 2 1 SIZE 0 - 75 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:19] [18:16] [15] [14] BASADDR RESERVED MRSET RESERVED Base address pointer of SDRAM bank 0/1 The start address is calculated as SDRAM bank 0/1 base pointer << 18. The SDRAM base address pointer together with the "SIZE" bits constitutes the whole address range of each SDRAM bank. SDRAM Mode register set command for SDRAM bank 0/1 This bit set will issue a mode register set command to SDRAM. Auto pre-charge mode of SDRAM for SDRAM bank 0/1 Enable the auto pre-charge function of external SDRAM bank 0/1 0 = Auto pre-charge 1 = No auto pre-charge The CAS Latency of SDRAM bank 0/1 Defines the CAS latency of external SDRAM bank 0/1 LATENCY [12:11] MCLK 1 2 3 REVERSED [13] AUTOPR [12:11] LATENCY 0 0 1 1 0 1 0 1 [10:8] RESERVED Number of component bank in SDRAM bank 0/1 Indicates the number of component bank (2 or 4 banks) in external SDRAM bank 0/1. 0 = 2 banks 1 = 4 banks Data bus width for SDRAM bank 0/1 Indicates the external data bus width connect with SDRAM bank 0/1 If DBWD = 00, the assigned SDRAM access signal is not generated i.e. disable. [7] COMPBK [6:5] DBWD DBWD [6:5] 0 0 1 1 0 1 0 1 Bits Bank disable 8-bit (byte) 16-bit (half-word) 32-bit (word) - 76 - W90P710 Continued. BITS DESCRIPTION Number of column address bits in SDRAM bank 0/1 Indicates the number of column address bits in external SDRAM bank 0/1. COLUMN [4:3] [4:3] COLUMN 0 0 1 1 0 1 0 1 Bits 8 9 10 REVERSED Size of SDRAM bank 0/1 Indicates the memory size of external SDRAM bank 0/1 SIZE [2:0] Size of SDRAM Byte 0 [2:0] SIZE 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bank disable 2M 4M 8M 16M 32M 64M REVERSED Timing Control Registers SDTIME0/1 W90P710 offers the flexible timing control registers to control the generation and processing of the control signals and can achieve you use different speed of SDRAM REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SDTIME0 SDTIME1 0xFFF0_1010 0xFFF0_1014 R/W SDRAM bank 0 timing control register R/W SDRAM bank 1 timing control register 0x0000_0000 0x0000_0000 - 77 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 RESERVED 15 14 13 RESERVED 7 tRDL 6 5 4 tRP 3 2 12 11 10 9 tRCD 1 tRAS 0 8 BITS DESCRIPTION [31:11] RESERVED SDRAM bank 0/1, /RAS to /CAS delay tRCD [10:8] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 MCLK 1 2 3 4 5 6 7 8 [10:8] tRCD [7:6] tRDL SDRAM bank 0/1, Last data in to pre-charge command tRDL [7:6] MCLK 0 0 1 0 1 2 1 0 3 1 1 4 SDRAM bank 0/1, Row pre-charge time tRP [5:3] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 [5:3] tRP - 78 - W90P710 Continued. BITS DESCRIPTION [2:0] tRAS SDRAM bank 0/1, Row active time tRAS [2:0] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 MCLK 1 2 3 4 5 6 7 8 Fig 7.3.4 Access timing 1 of SDRAM Fig 7.3.5 Access timing 2 of SDRAM - 79 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 External I/O Control RegistersEXT0CON - EXT3CON The W90P710 supports an external device control without glue logic. It is very cost effective because address decoding and control signals timing logic are not needed. Using these control registers you can configure special external I/O devices for providing the low cost external devices control solution. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EXT0CON EXT1CON EXT2CON EXT3CON 31 0xFFF0_1018 0xFFF0_101C 0xFFF0_1020 0xFFF0_1024 30 29 R/W External I/O 0 control register R/W External I/O 1 control register R/W External I/O 2 control register R/W External I/O 3 control register 28 BASADDR 27 26 25 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 24 23 22 21 BASADDR 20 19 18 17 SIZE 16 15 ADRS 7 14 13 tACC 12 11 10 9 tCOH 8 6 tACS 5 4 3 tCOS DESCRIPTION 2 1 DBWD 0 BITS [31:11] BASADDR [18:16] SIZE Base address pointer of external I/O bank 0~3 The start address of each external I/O bank is calculated as "BASADDR" base pointer << 18. Each external I/O bank base address pointer together with the "SIZE" bits constitutes the whole address range of each external I/O bank. The size of the external I/O bank 0~3 SIZE [18:16] Byte 0 0 0 256K 0 0 1 512K 0 1 0 1M 0 1 1 2M 1 0 0 4M 1 0 1 8M 1 1 0 16M 1 1 1 REVERSED - 80 - W90P710 Continued. BITS DESCRIPTION Address bus alignment for external I/O bank 0~3 [15] ADRS When ADRS is set, external address (A21~A0) bus is alignment to byte address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting. Access cycles of external I/O bank 0~3 This parameter means nWE, nWBE and nOE active time clock. Detail timing diagram please refer to Fig. 7.3.6 and 7.3.7 tACC[14:11] 0 0 [14:11] tACC 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MCLK Reversed 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 tACC[14:11] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MCLK 9 11 13 15 17 19 21 23 Chip selection hold time of external I/O bank 0~3 This parameters control nWBE and nOE hold time. Detail timing diagram please refer to Fig. 7.3.6 and 7.3.7 tCOH [10:8] 0 0 1 1 0 0 1 1 MCLK 0 1 2 3 4 5 6 7 [10:8] tCOH 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 - 81 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION Address set-up before nECS for external I/O bank 0~3 tACS [7:5] 0 0 1 1 0 0 1 1 MCLK 0 1 2 3 4 5 6 7 [7:5] tACS 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 Chip selection set-up time of external I/O bank 0~3 When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated. tCOS [4:2] 0 0 1 1 0 0 1 1 MCLK 0 1 2 3 4 5 6 7 [4:2] tCOS 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 Programmable data bus width for external I/O bank 0~3 DBWD [1:0] 0 0 0 1 1 0 1 1 Width of Data Bus Disable bus 8-bit 16-bit 32-bit [1:0] DBWD - 82 - W90P710 Fig 7.3.6 External I/O write operation timing Fig 7.3.7 External I/O read operation timing - 83 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 2Mx16 SRAM W90P710 A[21:0] D[31:0] nECSn nWE nOE nWBE_SDQM[1] nWBE_SDQM[0] A[21:0] DQ[15:0] nCS nWE nOE nUB nLB Fig. 7.3.8 External IO bank with 16-bit SRAM Clock Skew Control Register CKSKEW Register CKSKEW Address 0xFFF0_1F00 R/W R/W Description Clock skew control register Reset Value 0xXXXX_0018 31 30 29 28 27 26 25 24 DLH_CLK_REF 23 22 21 20 19 18 17 16 DLH_CLK_REF 15 14 13 12 RESVERED 7 6 5 4 3 2 MCLK_O_D 1 11 10 9 8 SWPON 0 DLH_CLK_SKEW - 84 - W90P710 BITS DESCRIPTION Latch DLH_CLK clock tree by HCLK positive edge [31:16] DLH_CLK_REF The SDRAM MCLK is generated by inserting a delay (XOR2) chain in HCLK positive or negedge edge to adjust the MCLK skew. So software can read these bits to expore MCLK and HCLK relationship. [31:24] is used for positive edge and [23:16] is for negedge edge. SDRAM Initialization by Software [8] SWPON Set this bit "1" will issue a SDRAM power on default setting command sequence like system power on, this bit will be auto-clear by hardware while SDRAM initialization finish. Data latch Clock Skew Adjustment Due to PC board loading or too many devices connect to external address and data bus, it may causes SDRAM can not work correctly at high frequency (usually, > 80MHz) software can control MCLK_O_D[3:0] to adjust address and data bus to adjust setup/hold time. DLH_CLK_SKEW[7:4] 0 [7:4] DLH_CLK_SKEW 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Gate Delay P-0 P-1 P-2 P-3 P-4 P-5 P-6 P-7 DLH_CLK_SKEW[7:4] 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Gate Delay N-0 N-1 N-2 N-3 N-4 N-5 N-6 N-7 [15:9] RESERVED NOTE: P-x means Data latched Clock shift "X" gates delays by refer MCLKO positive edge, N-x means Data latched Clock shift "X" gates delays by refer MCLKO negative edge. - 85 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION MCLK output delay adjustment MCLK_O_D [3:0] Gate Dela y 0 1 0 1 0 1 0 1 P-0 P-1 P-2 P-3 P-4 P-5 P-6 P-7 1 1 1 1 1 1 1 1 MCLK_O_D [3:0] Gate Dela y 0 1 0 1 0 1 0 1 N-0 N-1 N-2 N-3 N-4 N-5 N-6 N-7 0 0 0 [3:0] MCLK_O_D 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 NOTE: "P-x" means MCLKO shift "X" gates delay by refer HCLK positive edge, "N-x" means MCLKO shift "X" gates delay by refer HCLK negative edge. MCLK is the output pin of MCLKO, which is an internal signal on chip. - 86 - W90P710 7.4 Cache Controller The W90P710 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The ICache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these two caches are configured two-way set associative addressing. Each cache has four words cache line size. When a miss occurs, four words must be fetched consecutively from external memory. The replacement algorithm is a LRU (Least Recently Used). If disabling the I-Cache / D-Cache, these cache memories can be treated as On-Chip RAM. The W90P710 also provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data. 7.4.1 On-Chip RAM If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has 4KB On-Chip RAM, its start address is 0xFFE01000. If I-Cache is disabled, there has 4KB On-Chip RAM and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has 8KB On-Chip RAM starting from 0xFFE00000. The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in Cache Control Register (CAHCON). Table7.4.1 The size and start address of On-Chip RAM ICAEN DCAEN ON-CHIP RAM SIZE START ADDRESS 0 0 1 1 0 1 0 1 8KB 4KB 4KB 0xFFE0_0000 0xFFE0_0000 0xFFE0.1000 Unavailable 7.4.2 Non-Cacheable Area Although the cache affects the entire 2GB system memory, it is sometimes necessary to define noncacheable areas when the consistency of data stored in memory and the cache must be ensured. To support this, the W90P710 provides a non-cacheable area control bit in the address field, A[31]. If A[31] in the ROM/FLASH, SDRAM, or external I/O bank's access address is "0", then the accessed data is cacheable. If the A [31] value is "1", the accessed data is non-cacheable. - 87 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.4.3 Instruction Cache The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction request from the instruction unit in the core. In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The first word received from the bus is the requested instruction. The cache forwards this instruction to the instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When I-Cache is disabled, the cache memory is served as 4KB On-chip RAM. The I-Cache is always disabled on reset. The following is a list of the instruction cache features 4K bytes instruction cache Two-way set associative Four words in a cache line LRU replacement policy Lockable on a per-line basis Critical word first, burst access Instruction Cache Operation On an instruction fetch, bits 10-4 of the instruction's address point into the cache to retrieve the tags and data of one set. The tags from both ways are then compared against bits 30-11 of the instruction's address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is not valid, it is a cache miss. Instruction Cache Hit In case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line whose tag matches. The instruction is immediately transferred to the instruction unit of the core. Instruction Cache Miss On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4word burst transfer read request. A cache line is then selected to receive the data that will be coming from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the selected set is invalid, then the least recently used line is selected for replacement. Locked lines are never replaced. The transfer begins with the word requested by the instruction unit (critical word first), followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound). Instruction Cache Flushing The W90P710 does not support external memory snooping. Therefore, if self-modifying code is written, the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with the ICAH bit is set. As flushing the cache line, the "V" bit of the line is cleared to "0". The I-Cache is automatically flushed during reset. - 88 - W90P710 Instruction Cache Load and Lock The W90P710 supports a cache-locking feature that can be used to lock critical sections of code into ICache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line command. To load and lock instruction, the following sequence should be followed: 1. 2. 3. 4. 5. Write the start address of the instructions to be locked into CAHADR register. Set LDLK and ICAH bits in the CAHCON register. Increased the address by 16 and written into CAHADR register. Set LDLK and ICAH bits in the CAHCON register. Repeat the steps 3 and 4, until the desired instructions are all locked. When using I-Cache load and lock command, there are some notes should be cared. The programs executing load and lock operation should be held in a non-cacheable area of memory. The cache should be enabled and interrupts should be disabled. Software must flush the cache before execute load and lock to ensure that the code to be locked down is not already in the cache. Instruction Cache Unlock The unlock operation is used to unlock previously locked cache lines. After unlock, the "L" bit of the line is cleared to "0". W90P710 has two unlock command, unlock line and unlock all. The unlock line operation is performed on a cache line granularity. In case the line is found in the cache, it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the cache, no operation is done and the command terminates with no exception. To unlock one line the following unlock line sequence should be followed: 1. 2. Write the address of the line to be unlocked into the CAHADR Register. Set the ULKS and ICAH bits in the CAHCON register. The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA and ICAH bits. - 89 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.4.4 Data Cache The W90P710 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache is designed for buffer write-through mode of operation and a least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM. The D-Cache is always disabled on reset. The following is a list of the data cache features 4K bytes data cache Two-way set associative Four words in a cache line LRU replacement policy Lockable on a per-line basis Critical word first, burst access Buffer Write-through mode 8 words write buffer Drain write buffer Data Cache Operation On a data fetch, bits 10-4 of the data's address point into the cache to retrieve the tags and data of one set. The tags from both ways are then compared against bits 30-11 of the data's address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is not valid, it is a cache miss. Data Cache Read Read HitOn a cache hit, the requested word is immediately transferred to the core. Read MissA line in the cache is selected to hold the data, which will be fetched from memory. The selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the missed data (critical word first), followed by the remaining word in the line, then by the word at the beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to the core. Data Cache Write As buffer write-through mode, store operations always update memory. The buffer write-through mode is used when external memory and internal cache images must always agree. - 90 - W90P710 Write HitData is written into both the cache and write buffer. The processor then continues to access the cache, while the cache controller simultaneously downloads the contents of the write buffer to main memory. This reduces the effective write memory cycle time from the time required for a main memory cycle to the cycle time of the high-speed cache. Write MissData is only written into write buffer, not to the cache (write no allocate). Data Cache Flushing The W90P710 allows flushing of the data cache under software control. The data cache may be invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register. Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the "V" bit of the line is cleared to "0". The D-cache is automatically flushed during reset. Data Cache Load and Lock The W90P710 supports a cache-locking feature that can be used to lock critical sections of data into DCache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction SRAM. The locked lines are not replaced during misses and it is not affected by flush per line command. To load and lock data, the following sequence should be followed: 1. 2. 3. 4. 5. Write the start address of the data to be locked into CAHADR register. Set LDLK and DCAH bits in the CAHCON register. Increased the address by 16 and written into CAHADR register. Set LDLK and DCAH bits in the CAHCON register. Repeat the steps 3 and 4, until the desired data are all locked. When using D-Cache load and lock command, there are some notes should be cared. The programs executing load and lock operation should be held in a non-cacheable area of memory. The cache should be enabled and interrupts should be disabled. Software must flush the cache before execute load and lock to ensure that the data to be locked down is not already in the cache. Data Cache Unlock The unlock operation is used to unlock previously locked cache lines. After unlock, the "L" bit of the line is cleared to "0". W90P710 has two unlock command, unlock line and unlock all. The unlock line operation is performed on a cache line granularity. In case the line is found in the cache, it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the cache, no operation is done and the command terminates with no exception. To unlock one line the following unlock line sequence should be followed: 1. 2. Write the address of the line to be unlocked into the CAHADR Register. Set the ULKS and DCAH bits in the CAHCON register. - 91 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA and DCAH bits. 7.4.5 Write Buffer The W90P710 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF register, and the buffer is disabled and flushed on reset. Drain write buffer To force data, this is in write buffer, to be written to external main memory. This operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues. To perform this command, you can set the DRWB and DCAH bits in CAHCON register. 7.4.6 Cache Control Registers Map ADDRESS R/W DESCRIPTION RESET VALUE REGISTER CAHCNF CAHCON CAHADR CTEST0 CTEST1 0xFFF0_2000 0xFFF0_2004 0xFFF0_2008 0xFFF6_0000 0xFFF6_0004 R/W Cache configuration register R/W Cache control register R/W Cache address register R/W Cache test register 0 R Cache test register 1 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Configuration Register (CAHCNF) Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write buffer. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCNF 0xFFF0_2000 R/W Cache configuration register 0x0000_0000 - 92 - W90P710 31 30 29 28 RESERVED 27 26 25 24 23 22 21 20 RESERVED 19 18 17 16 15 14 13 12 RESERVED 11 10 9 8 7 6 5 RESERVED 4 3 2 WRBEN 1 DCAEN 0 ICAEN BITS DESCRIPTION [31:3] RESERVED Write buffer enable Write buffer is disabled after reset. 1 = enable write buffer 0 = disable write buffer D-Cache enable D-Cache is disabled after reset. 1 = enable D-cache 0 = disable D-cache I-Cache enable I-Cache is disabled after reset. 1 = enable I-cache 0 = disable I-cache [2] WRBEN [1] DCAEN [0] ICAEN Control Register (CAHCON) Cache controller supports one Control register used to control the following operations. Flush I-Cache and D-Cache Load and lock I-Cache and D-Cache Unlock I-Cache and D-Cache Drain write buffer These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command set bit will be cleared to "0" automatically. - 93 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCON 0xFFF0_2004 30 29 R/W Cache control register 0x0000_0000 26 25 24 31 28 RESERVED 27 23 22 21 20 RESERVED 19 18 17 16 15 14 13 12 RESERVED 11 10 9 8 7 DRWB 6 ULKS 5 ULKA 4 LDLK 3 FLHS 2 FLHA 1 DCAH 0 ICAH BITS DESCRIPTION [31:8] [7] RESERVED DRWB Drain write buffer Forces write buffer data to be written to main memory. Unlock I-Cache/D-Cache single line Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. Unlock I-Cache/D-Cache entirely Unlocks the entire I-Cache/D-Cache, the lock bit "L" will be cleared to 0. Load and Lock I-Cache/D-Cache Loads the instruction or data from external memory and locks into cache. Both WAY and ADDR bits in CAHADR register must be specified. Flush I-Cache/D-Cache single line Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. Flush I-Cache/D-Cache entirely To flush the entire I-Cache/D-Cache, also flushes any locked-down code. If the I-Cache/D-Cache contains locked down code, the programmer must flush lines individually D-Cache selected When set to "1", the command set is executed with D-Cache. I-Cache selected When set to "1", the command set is executed with I-Cache. [6] ULKS [5] ULKA [4] LDLK [3] FLHS [2] FLHA [1] [0] DCAH ICAH - 94 - W90P710 NOTEWhen using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid command and no operation is done and the command terminates with no exception. The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no operation is done and the command terminates with no exception. Address Register (CAHADR) W90P710 Cache Controller supports one address register. This address register is used with the command set in the control register (CAHCON) by specifying instruction/data address. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000 31 WAY 23 30 29 28 27 ADDR 26 25 24 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 BITS DESCRIPTION Way selection [31] [30:0] WAY ADDR 0 = Way0 is selected 1 = Way1 is selected The absolute address of instruction or data - 95 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Cache Test Register 0 (CTEST0) Cache test control register that configures the cache and tag ram testing enable or disable. In addition, this register controls the built-in-self-test (BIST) function of SRAM. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CTEST0 31 0xFFF6_0000 30 29 R/W Cache test register 0 28 RESERVED 27 26 25 0x0000_0000 24 23 22 21 20 RESERVED 19 18 17 16 15 BISTEN 7 14 13 RESERVED 12 11 BST_GP3 10 9 8 BST_GP2 BST_GP1 BST_GP0 2 1 0 CATEST 6 5 4 RESERVED 3 BITS DESCRIPTION [31:16] [15] [14:12] [11] RESERVED BISTEN RESERVED BIST_GP3 BIST mode enable When set to "1", BIST mode will be enabled, the selected memory groups begins to be tested by BIST. Memory group 3 is selected to test by BIST When set to "1", memory group 3, including data cache tag ram way 0 and way 1, are selected to be tested by BIST. Memory group 2 is selected to test by BIST When set to "1", memory group 2, including program cache tag ram way 0 and way 1, are selected to be tested by BIST. Memory group 1 is selected to test by BIST When set to "1", memory group 1, including data cache ram way 0 and way 1, are selected to be tested by BIST. Memory group 0 is selected to test by BIST When set to "1", memory group 0, including program cache ram way 0 and way 1, are selected to be tested by BIST. - [10] BIST_GP2 [9] BIST_GP1 [8] [7:0] BIST_GP0 RESERVED ** Note: The 4 memory groups can be selected and tested simultaneously by BIST. - 96 - W90P710 Cache Test Register 1 (CTEST1) Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST is finish and all of bank of SRAM are tested successfully will be presented in this register. Register CTEST1 31 FINISH 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 BFAIL7 6 BFAIL6 5 BFAIL5 4 BFAIL4 3 BFAIL3 2 BFAIL2 1 BFAIL1 0 BFAIL0 11 10 9 8 Address 0xFFF6_0004 30 29 R/W R Description Cache test register 1 28 27 RESERVED 19 18 17 16 26 25 Reset Value 0x0000_0000 24 BITS DESCRIPTION BIST completed [31] [30:8] [7] FINISH RESERVED BFAIL7 This bit is "0" initially. When BIST mode enabled, this bit will be "1" after BIST test completed. The values of BFAIL0-7 are valid only after FINISH = 1. BIST test fail for data cache tag ram way 1 If this bit equals to "1", it indicates the data cache tag ram for way 1 is tested fail by BIST. "0" means the test is passed. BIST test fail for data cache tag ram way 0 [6] BFAIL6 If this bit equals to "1", it indicates the data cache tag ram for way 0 is tested fail by BIST. "0" means the test is passed. BIST test fail for instruction cache tag ram way 1 [5] BFAIL5 If this bit equals to "1", it indicates the instruction cache tag ram for way 1 is tested fail by BIST. "0" means the test is passed. BIST test fail for instruction cache tag ram way 0 [4] BFAIL4 If this bit equals to "1", it indicates the instruction cache tag ram for way 0 is tested fail by BIST. "0" means the test is passed. BIST test fail for data cache ram way 1 [3] BFAIL3 If this bit equals to "1", it indicates the data cache ram for way 1 is tested fail by BIST. "0" means the test is passed. Publication Release Date: January 17, 2005 Revision A.2 - 97 - W90P710 Continued. BITS DESCRIPTION BIST test fail for data cache ram way 0 [2] BFAIL2 If this bit equals to "1", it indicates the data cache ram for way 0 is tested fail by BIST. "0" means the test is passed. BIST test fail for instruction cache ram way 1 [1] BFAIL1 If this bit equals to "1", it indicates the instruction cache ram for way 1 is tested fail by BIST. "0" means the test is passed. BIST test fail for instruction cache ram way 0 [0] BFAIL0 If this bit equals to "1", it indicates the instruction cache ram for way 0 is tested fail by BIST. "0" means the test is passed. 7.5 Ethernet MAC Controller Overview The W90P710 provides an Ethernet MAC Controller (EMC) for LAN application. This EMC has its DMA controller, transmit FIFO, and receive FIFO. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller and status controller. The EMC only supports RMII (Reduced MII) interface to connect with PHY operating on 50MHz REF_CLK. Features Supports IEEE Std. 802.3 CSMA/CD protocol. Supports both half and full duplex for 10M/100M bps operation. Supports RMII interface. Supports MII Management function. Supports pause and remote pause function for flow control. Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception. Supports 16 entries CAM function for Ethernet MAC address recognition. Supports internal loop back mode for diagnostic. Supports 256 bytes embedded transmit and receive FIFO. Supports DMA function. - 98 - W90P710 7.5.1 EMC Functional Description MII Management State Machine The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management interface, software can access the control and status registers of the external PHY chip. Tow programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII Management Data Control and Address Register) are for MII management function. Set the bit BUSY of MIIDA register will trigger the MII management state machine. After the MII management cycle is finished, the BUSY bit will be cleared automatically. Media Access Control (MAC) The function of W90P710 MAC fully meets the requirements defined by the IEEE802.3u specification. The following paragraphs will describe the frame structure and the operation of the transmission and receive. The transmission data frame sent from the transmit DMA will be encapsulated by the MAC before transmitting onto the MII bus. The sent data will be assembled with the preamble, the start frame delimiter (SFD), the frame check sequence and the padding for enforcing those less than 64 bytes to meet the minimum size frame and CRC sequence. The out going frame format will be as following 110101010 --- 10101010 10101011 d0 d1 d2 dn Padding CRC31 CRC30 --CRC0 As mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern "10101010" and the SFD is a one byte 10101011 data. The padding data will be all 0 value if the sent data frame is less than 64 bytes. The padding disable function specified in the bit P of the transmit descriptor is used to control if the MAC needs to pad data at the end of frame data or not when the transmitted data frame is less than 64 bytes. The padding data will not be appended if the padding disable bit is set to be high. The bits CRC0 ... CRC31 are the 32 bits cyclic redundancy check (CRC) sequence. The CRC encoding is defined by the following polynomial specified by the IEEE802.3. This 32 bits CRC appending function will be disabled if the Inhibit CRC of the transmission descriptor is set to high. The MAC also performs many other transmission functions specified by the IEEE802.3, including the inter-frame spacing function, collision detection, collision enforcement, collision back off and retransmission. The collision back-off timer is a function of the integer slot time, 512 bit times. The number of slot times to delay between the current transmissions attempts to the next attempt is determined by a uniformly distributed random integer algorithm specified by the IEEE802.3. The MAC performs the receive functions specified by the IEEE 802.3 including the address recognition function, the frame check sequence validation, the frame disassembly, framing and collision filtering. - 99 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 EMC Descriptors A link-list data structure named as descriptor is used to keep the control, status and data information of each frame. Through the descriptor, CPU and EMC exchange the information for frame reception and transmission. Two different descriptors are defined in W90P710. One named as Rx descriptor for frame reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of four words. There is much information kept in the descriptors and details are described as below. 7.5.1.1. Rx Buffer Descriptor 332 109 O Rx Status Receive Buffer Starting Address Reserved 11 65 Receive Byte Count 0 BO Next Rx Descriptor Starting Address Rx Descriptor Word 0 31 Owner 23 Reserved 15 7 22 RP 14 6 21 ALIE 13 5 20 RXGD 12 RBC 4 RBC Owner [31:30]: Ownership The ownership field defines which one, the CPU or EMC, is the owner of each Rx descriptor. Only the owner has right to modify the Rx descriptor and the others can read the Rx descriptor only. 00: The owner is CPU 01: Undefined 10: The owner is EMC 11: Undefined If the O=2'b10 indicates the EMC RxDMA is the owner of Rx descriptor and the Rx descriptor is available for frame reception. After the frame reception completed, if the frame needed NAT translation, EMC RxDMA modify ownership field to 2'b11. Otherwise, the ownership field will be modified to 2'b00. 3 2 1 0 19 PTLE 11 30 29 28 27 26 Reserved 18 Reserved 10 17 CRCE 9 16 RXINTR 8 25 24 - 100 - W90P710 If the O=2'b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing the frame, it modifies the ownership field to 2'b10 and releases the Rx descriptor to EMC RxDMA. Rx Status [29:16]: Receive Status This field keeps the status for frame reception. All status bits are updated by EMC. In the receive status, bits 29 to 23 are undefined and reserved for the future. RP [22]: Runt Packet The RP indicates the frame stored in the data buffer pointed by Rx descriptor is a short frame (frame length is less than 64 bytes). 1'b0: The frame is not a short frame. 1'b1: The frame is a short frame. ALIE [21]: Alignment Error The ALIE indicates the frame stored in the data buffer pointed by Rx descriptor is not a multiple of byte. 1'b0: The frame is a multiple of byte. 1'b1: The frame is not a multiple of byte. RXGD [20]: Frame Reception Complete The RXGD indicates the frame reception has completed and stored in the data buffer pointed by Rx descriptor. 1'b0: The frame reception not complete yet. 1'b1: The frame reception completed. PTLE [19]: Packet Too Long The PTLE indicates the frame stored in the data buffer pointed by Rx descriptor is a long frame (frame length is greater than 1518 bytes). 1'b0: The frame is not a long frame. 1'b1: The frame is a long frame. CRCE [17]: CRC Error The CRCE indicates the frame stored in the data buffer pointed by Rx descriptor incurred CRC error. 1'b0: The frame doesn't incur CRC error. 1'b1: The frame incurred CRC error. - 101 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 RXINTR [16]: Receive Interrupt The RXINTR indicates the frame stored in the data buffer pointed by Rx descriptor caused an interrupt condition. 1'b0: The frame doesn't cause an interrupt. 1'b1: The frame caused an interrupt. RBC [15:0]: Receive Byte Count The RBC indicates the byte count of the frame stored in the data buffer pointed by Rx descriptor. The four bytes CRC field is also included in the receive byte count. But if the SPCRC of register MCMDR is enabled, the four bytes CRC field will be excluded from the receive byte count. Rx Descriptor Word 1 31 23 15 7 30 22 14 6 29 21 13 5 RXBSA RXBSA [31:2]: Receive Buffer Starting Address The RXBSA indicates the starting address of the receive frame buffer. The RXBSA is used to be the bit 31 to 2 of memory address. In other words, the starting address of the receive frame buffer always located at word boundary. BO [1:0]: Byte Offset The BO indicates the byte offset from RXBSA where the received frame begins to store. If the BO is 2'b01, the starting address where the received frame begins to store is RXBSA+2'b01, and so on. 28 RXBSA 20 RXBSA 12 RXBSA 4 3 2 1 BO 0 11 10 9 8 19 18 17 16 27 26 25 24 - 102 - W90P710 Rx Descriptor Word 2 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved The Rx descriptor word 2 keeps obsolete information for MAC translation. Therefore, these information bits are undefined and should be ignored. 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Rx Descriptor Word 3 31 23 15 7 30 22 14 6 29 21 13 5 28 NRXDSA 20 NRXDSA 12 NRXDSA 4 NRXDSA 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 NRXDSA [31:0]: Next Rx Descriptor Starting Address The Rx descriptor is a link-list data structure. Consequently, NRXDSA is used to keep the starting address of the next Rx descriptor. The bits [1:0] will be ignored by EMC. So, all Rx descriptor must locate at word boundary memory address. - 103 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.5.1.2. Tx Buffer Descriptor 33 10 O 11 65 Reserved 3210 I CP BO Transmit Buffer Starting Address Tx Status Transmit Byte Count Next Tx Descriptor Starting Address Tx Descriptor Word 0 31 Owner 23 15 7 22 14 6 21 13 5 Reserved Owner [31]: Ownership The ownership field defines which one, the CPU or EMC, is the owner of each Tx descriptor. Only the owner has right to modify the Tx descriptor and the other can read the Tx descriptor only. 0: The owner is CPU 1: The owner is EMC If the O=1'b1 indicates the EMC TxDMA is the owner of Tx descriptor and the Tx descriptor is available for frame transmission. After the frame transmission completed, EMC TxDMA modify ownership field to 1'b0 and return the ownership of Tx descriptor to CPU. If the O=1'b0 indicates the CPU is the owner of Tx descriptor. After the CPU prepares new frame to wait transmission, it modifies the ownership field to 1'b1 and releases the Tx descriptor to EMC TxDMA. IntEn [2]: Transmit Interrupt Enable The IntEn controls the interrupt trigger circuit after the frame transmission completed. If the IntEn is enabled, the EMC will trigger interrupt after frame transmission completed. Otherwise, the interrupt doesn't be triggered. 1'b0: Frame transmission interrupt is masked. 1'b1: Frame transmission interrupt is enabled. 20 12 4 30 29 28 27 Reserved 19 Reserved 11 Reserved 3 2 IntEn 1 CRCApp 0 PadEn 10 9 8 18 17 16 26 25 24 - 104 - W90P710 CRCApp [1]: CRC Append The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes CRC checksum will be appended to frame at the end of frame transmission. 1'b0: 4-bytes CRC appending is disabled. 1'b1: 4-bytes CRC appending is enabled. PadEN [0]: Padding Enable The PadEN control the PAD bits appending while the length of transmission frame is less than 60 bytes. If PadEN is enabled, EMC does the padding automatically. 1'b0: PAD bits appending is disabled. 1'b1: PAD bits appending is enabled. Tx Descriptor Word 1 31 23 15 7 30 22 14 6 29 21 13 5 TXBSA TXBSA [31:2]: Transmit Buffer Starting Address The TXBSA indicates the starting address of the transmit frame buffer. The TXBSA is used to be the bit 31 to 2 of memory address. In other words, the starting address of the transmit frame buffer always located at word boundary. BO [1:0]: Byte Offset The BO indicates the byte offset from TXBSA where the transmit frame begins to read. If the BO is 2'b01, the starting address where the transmit frame begins to read is TXBSA+2'b01, and so on. 28 TXBSA 20 TXBSA 12 TXBSA 4 3 2 1 BO 0 11 10 9 8 19 18 17 16 27 26 25 24 - 105 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Tx Descriptor Word 2 31 23 LC 15 7 30 CCNT 22 TXABT 14 6 21 NCS 13 5 20 EXDEF 12 TBC 4 TBC CCNT [31:28]: Collision Count The CCNT indicates the how many collision occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4'h0 and bit TXABT will be set to 1. SQE [26]: SQE Error The SQE indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. The SQE error check will only be done while both bit EnSQE of MCMDR is enabled and EMC is operating on 10Mbps half-duplex mode. 1'b0: No SQE error found at end of packet transmission. 1'b0: SQE error found at end of packet transmission. PAU [25]: Transmission Paused THE PAU INDICATES THE NEXT NORMAL PACKET transmission process will be paused temporally because EMC received a PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to transmit a PAUSE control frame out. 1'b0: Next normal packet transmission process will go on. 1'b1: Next normal packet transmission process will be paused. TXHA [24]: Transmission Halted The TXHA indicates the next normal packet transmission process will be halted because the bit TXON of MCMDR is disabled be S/W. 1'b0: Next normal packet transmission process will go on. 1'b1: Next normal packet transmission process will be halted. 3 2 1 0 29 28 27 Reserved 26 SQE 18 Reserved 25 PAU 17 DEF 9 24 TXHA 16 TXINTR 8 19 TXCP 11 10 - 106 - W90P710 LC [23]: Late Collision The LC indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. 1'b0: No collision occurred in the outside of 64 bytes collision window. 1'b1: Collision occurred in the outside of 64 bytes collision window. TXABT [22]: Transmission Abort The TXABT indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMC is operating on half-duplex mode. 1'b0: Packet doesn't incur 16 consecutive collisions during transmission. 1'b1: Packet incurred 16 consecutive collisions during transmission. NCS [21]: No Carrier Sense The NCS indicates the MII I/F signal CRS doesn't active at the start of or during the packet transmission. The NCS is only available while EMC is operating on half-duplex mode. 1'b0: CRS signal actives correctly. 1'b1: CRS signal doesn't active at the start of or during the packet transmission. EXDEF [20]: Defer Exceed The EXDEF indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NDEF of MCMDR is disabled, and EMC is operating on half-duplex mode. 1'b0: Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). 1'b1: Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). TXCP [19]: Transmission Complete The TXCP indicates the packet transmission has completed correctly. 1'b0: The packet transmission doesn't complete. 1'b1: The packet transmission has completed. DEF [17]: Transmission Deferred The DEF indicates the packet transmission has deferred once. The DEF is only available while EMC is operating on half-duplex mode. 1'b0: Packet transmission doesn't defer. 1'b1: Packet transmission has deferred once. - 107 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 TXINTR [16]: Transmit Interrupt The TXINTR indicates the packet transmission caused an interrupt condition. 1'b0: The packet transmission doesn't cause an interrupt. 1'b1: The packet transmission caused an interrupt. TBC [15:0]: Transmit Byte Count The TBC indicates the byte count of the frame stored in the data buffer pointed by Tx descriptor for transmission. Tx Descriptor Word 3 31 23 15 7 30 22 14 6 29 21 13 5 28 NTXDSA 20 NTXDSA 12 NTXDSA 4 NTXDSA NTXDSA [31:0]: Next Tx Descriptor Starting Address The Tx descriptor is a link-list data structure. Consequently, NTXDSA is used to keep the starting address of the next Tx descriptor. The bits [1:0] will be ignored by EMC. So, all Tx descriptor must locate at word boundary memory address. 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 - 108 - W90P710 7.5.2 EMC Register Mapping The EMC implements many registers and the registers are separated into three types, the control registers, the status registers and diagnostic registers. The control registers are used by S/W to pass control information to EMC. The status registers are used to keep EMC operation status for S/W. And, the diagnostic registers are used for debug only. EMC Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CONTROL REGISTERS (44) CAMCMR CAMEN CAM0M CAM0L CAM1M CAM1L CAM2M CAM2L CAM3M CAM3L CAM4M CAM4L CAM5M CAM5L CAM6M CAM6L CAM7M CAM7L CAM8M CAM8L CAM9M CAM9L CAM10M CAM10L CAM11M CAM11L 0xFFF0_3000 0xFFF0_3004 0xFFF0_3008 0xFFF0_300C 0xFFF0_3010 0xFFF0_3014 0xFFF0_3018 0xFFF0_301C 0xFFF0_3020 0xFFF0_3024 0xFFF0_3028 0xFFF0_302C 0xFFF0_3030 0xFFF0_3034 0xFFF0_3038 0xFFF0_303C 0xFFF0_3040 0xFFF0_3044 0xFFF0_3048 0xFFF0_304C 0xFFF0_3050 0xFFF0_3054 0xFFF0_3058 0xFFF0_305C 0xFFF0_3060 0xFFF0_3064 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CAM Command Register CAM Enable Register CAM0 Most Significant Word Register CAM0 Least Significant Word Register CAM1 Most Significant Word Register CAM1 Least Significant Word Register CAM2 Most Significant Word Register CAM2 Least Significant Word Register CAM3 Most Significant Word Register CAM3 Least Significant Word Register CAM4 Most Significant Word Register CAM4 Least Significant Word Register CAM5 Most Significant Word Register CAM5 Least Significant Word Register CAM6 Most Significant Word Register CAM6 Least Significant Word Register CAM7 Most Significant Word Register CAM7 Least Significant Word Register CAM8 Most Significant Word Register CAM8 Least Significant Word Register CAM9 Most Significant Word Register CAM9 Least Significant Word Register CAM10 Most Significant Word Register CAM10 Least Significant Word Register CAM11 Most Significant Word Register CAM11 Least Significant Word Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 109 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CONTROL REGISTERS (44) CAM12M CAM12L CAM13M CAM13L CAM14M CAM14L CAM15M CAM15L TXDLSA RXDLSA MCMDR MIID MIIDA FFTCR TSDR RSDR DMARFC MIEN MISTA MGSTA MPCNT MRPC MRPCC MREPC DMARFS 0xFFF0_3068 0xFFF0_306C 0xFFF0_3070 0xFFF0_3074 0xFFF0_3078 0xFFF0_307C 0xFFF0_3080 0xFFF0_3084 0xFFF0_3088 0xFFF0_308C 0xFFF0_3090 0xFFF0_3094 0xFFF0_3098 0xFFF0_309C 0xFFF0_30A0 0xFFF0_30A4 0xFFF0_30A8 0xFFF0_30AC 0xFFF0_30B0 0xFFF0_30B4 0xFFF0_30B8 0xFFF0_30BC 0xFFF0_30C0 0xFFF0_30C4 0xFFF0_30C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R R R R/W CAM12 Most Significant Word Register CAM12 Least Significant Word Register CAM13 Most Significant Word Register CAM13 Least Significant Word Register CAM14 Most Significant Word Register CAM14 Least Significant Word Register CAM15 Most Significant Word Register CAM15 Least Significant Word Register Transmit Descriptor Link List Start Address Register Receive Descriptor Link List Start Address Register MAC Command Register MII Management Data Register MII Management Control and Address Register FIFO Threshold Control Register Transmit Start Demand Register Receive Start Demand Register Maximum Receive Frame Control Register MAC Interrupt Enable Register MAC Interrupt Status Register MAC General Status Register Missed Packet Count Register MAC Receive Pause Count Register MAC Receive Pause Current Count Register MAC Remote Pause Count Register DMA Receive Frame Status Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFFF_FFFC 0xFFFF_FFFC 0x0000_0000 0x0000_0000 0x0090_0000 0x0000_0101 Undefined Undefined 0x0000_0800 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_7FFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Status Registers (11) - 110 - W90P710 Continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE Status Registers (11) CTXDSA CTXBSA CRXDSA CRXBSA 0xFFF0_30CC 0xFFF0_30D0 0xFFF0_30D4 0xFFF0_30D8 R R R R Current Transmit Descriptor Start Address Register Current Transmit Buffer Start Address Register Current Receive Descriptor Start Address Register Current Receive Buffer Start Address Register Receive Finite State Machine Register Transmit Finite State Machine Register Finite State Machine Register 0 Finite State Machine Register 1 Debug Configuration Register Debug Mode MAC Information Register BIST Mode Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Diagnostic Registers (7) RXFSM TXFSM FSM0 FSM1 DCR DMMIR BISTR 0xFFF0_3200 0xFFF0_3204 0xFFF0_3208 0xFFF0_320C 0xFFF0_3210 0xFFF0_3214 0xFFF0_3300 R R R R R/W R R/W 0x0081_1101 0x0101_1101 0x0001_0101 0x1100_0100 0x0000_003F 0x0000_0000 0x0000_0000 - 111 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.5.2.1. Register Details CAM Command Register (CAMCMR) The EMC of W90P710 supports CAM function for destination MAC address recognition. The CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet reception. Register CAMCMR Address 0xFFF0_3000 R/W R/W Description CAM Command Register Reset Value 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 20 12 4 ECMP 27 Reserved 19 Reserved 11 Reserved 3 CCAM 26 18 10 2 ABP 25 17 9 1 AMP 24 16 8 0 AUP BITS DESCRIPTIONS [31:5] Reserved The ECMP(Enable CAM Compare) controls the enable of CAM comparison function for destination MAC address recognition. If S/W wants to receive a packet with specific destination MAC address, configures the MAC address into anyone of 16 CAM entries, then enables that CAM entry and set ECMP to 1. 1'b0: Disable CAM comparison function for destination MAC address recognition. 1'b1: Enable CAM comparison function for destination MAC address recognition. The CCAM(Complement CAM Compare) controls the complement of the CAM comparison result. If the ECMP and CCAM are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped. And the incoming packet with destination MAC address doesn't configured in any CAM entry will be received. 1'b0: The CAM comparison result doesn't be complemented. 1'b1: The CAM comparison result will be complemented. [4] ECMP [3] CCAM - 112 - W90P710 Continued. BITS DESCRIPTIONS [2] ABP The Accept Broadcast Packet controls the broadcast packet reception. If ABP is enabled, EMC receives all incoming packet it's destination MAC address is a broadcast address. 1'b0: EMC receives packet depends on the CAM comparison result. 1'b1: EMC receives all broadcast packets. The Accept Multicast Packet controls the multicast packet reception. If AMP is enabled, EMC receives all incoming packet it's destination MAC address is a multicast address. 1'b0: EMC receives packet depends on the CAM comparison result. 1'b1: EMC receives all multicast packets. The Accept Unicast Packet controls the unicast packet reception. If AUP is enabled, EMC receives all incoming packet it's destination MAC address is a unicast address. 1'b0: EMC receives packet depends on the CAM comparison result. 1'b1: EMC receives all unicast packets. [1] AMP [0] AUP CAMCMR Setting and Comparison Result CAMCMR Setting and Comparison Result The following table is the address recognition result in different CAMCMR configuration. The column Result shows the incoming packet type that can pass the address recognition in specific CAM configuration. The C, U, M and B represents the: C: It indicates the destination MAC address of incoming packet has been configured in CAM entry. U: It indicates the incoming packet is a unicast packet. M: It indicates the incoming packet is a multicast packet. B: It indicates the incoming packet is a broadcast packet. - 113 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 ECMP CCAM AUP AMP ABP RESULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B M M C C C C C C C C C C C C C C C C C C C C U U U U C C C C No Packet B U U U U U U U U U U U U B M N U U U U M M M M U U U U B M M B B B B M M M M B B B B B B B M M M M M M M M M M B B B B B B B B B - 114 - W90P710 CAM Enable Register (CAMEN) The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before it can participate in the destination MAC address recognition. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAMEN 31 23 15 7 CAM7EN 0xFFF0_3004 30 22 14 6 CAM6EN 29 21 13 5 R/W CAM Enable Register 28 Reserved 20 Reserved 12 4 CAM4EN 11 3 CAM3EN 10 2 CAM2EN 9 19 18 17 27 26 25 0x0000_0000 24 16 8 CAM8EN 0 CAM0EN CAM15EN CAM14EN CAM13EN CAM12EN CAM11EN CAM10EN CAM5EN CAM9EN 1 CAM1EN BITS DESCRIPTIONS [31:16] CAM15EN Reserved The CAM entry 13, 14 and 15 are for PAUSE control frame transmission. If S/W wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first. CAM entry 12 is enabled [15:13] CAM14EN CAM13EN [12] CAM12EN 1'b0: CAM entry 12 disabled. 1'b1: CAM entry 12 enabled. CAM entry 11 is enabled [11] CAM11EN 1'b0: CAM entry 11 disabled. 1'b1: CAM entry 11 enabled. CAM entry 10 is enabled [10] CAM10EN 1'b0: CAM entry 10 disabled. 1'b1: CAM entry 10 enabled. - 115 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS CAM entry 9 is enabled [9] CAM9EN 1'b0: CAM entry 9 disabled. 1'b1: CAM entry 9 enabled. CAM entry 8 is enabled [8] CAM8EN 1'b0: CAM entry 8 disabled. 1'b1: CAM entry 8 enabled. CAM entry 7 is enabled [7] CAM7EN 1'b0: CAM entry 7 disabled. 1'b1: CAM entry 7 enabled. CAM entry 6 is enabled [6] CAM6EN 1'b0: CAM entry 6 disabled. 1'b1: CAM entry 6 enabled. CAM entry 5 is enabled [5] CAM5EN 1'b0: CAM entry 5 disabled. 1'b1: CAM entry 5 enabled. CAM entry 4 is enabled [4] CAM4EN 1'b0: CAM entry 4 disabled. 1'b1: CAM entry 4 enabled. CAM entry 3 is enabled [3] CAM3EN 1'b0: CAM entry 3 disabled. 1'b1: CAM entry 3 enabled. CAM entry 2 is enabled [2] CAM2EN 1'b0: CAM entry 2 disabled. 1'b1: CAM entry 2 enabled. CAM entry 1 is enabled [1] CAM1EN 1'b0: CAM entry 1 disabled. 1'b1: CAM entry 1 enabled. CAM entry 0 is enabled [0] CAM0EN 1'b0: CAM entry 0 disabled. 1'b1: CAM entry 0 enabled. - 116 - W90P710 CAM Entry Registers (CAMxx) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM0M CAM0L CAM1M CAM1L CAM2M CAM2L CAM3M CAM3L CAM4M CAM4L CAM5M CAM5L CAM6M CAM6L CAM7M CAM7L CAM8M CAM8L CAM9M CAM9L CAM10M CAM10L CAM11M CAM11L CAM12M CAM12L CAM13M CAM13L CAM14M CAM14L CAM15M CAM15L 0xFFF0_3008 0xFFF0_300C 0xFFF0_3010 0xFFF0_3014 0xFFF0_3018 0xFFF0_301C 0xFFF0_3020 0xFFF0_3024 0xFFF0_3028 0xFFF0_302C 0xFFF0_3030 0xFFF0_3034 0xFFF0_3038 0xFFF0_303C 0xFFF0_3040 0xFFF0_3044 0xFFF0_3048 0xFFF0_304C 0xFFF0_3050 0xFFF0_3054 0xFFF0_3058 0xFFF0_305C 0xFFF0_3060 0xFFF0_3064 0xFFF0_3068 0xFFF0_306C 0xFFF0_3070 0xFFF0_3074 0xFFF0_3078 0xFFF0_307C 0xFFF0_3080 0xFFF0_3084 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CAM0 Most Significant Word Register CAM0 Least Significant Word Register CAM1 Most Significant Word Register CAM1 Least Significant Word Register CAM2 Most Significant Word Register CAM2 Least Significant Word Register CAM3 Most Significant Word Register CAM3 Least Significant Word Register CAM4 Most Significant Word Register CAM4 Least Significant Word Register CAM5 Most Significant Word Register CAM5 Least Significant Word Register CAM6 Most Significant Word Register CAM6 Least Significant Word Register CAM7 Most Significant Word Register CAM7 Least Significant Word Register CAM8 Most Significant Word Register CAM8 Least Significant Word Register CAM9 Most Significant Word Register CAM9 Least Significant Word Register CAM10 Most Significant Word Register CAM10 Least Significant Word Register CAM11 Most Significant Word Register CAM11 Least Significant Word Register CAM12 Most Significant Word Register CAM12 Least Significant Word Register CAM13 Most Significant Word Register CAM13 Least Significant Word Register CAM14 Most Significant Word Register CAM14 Least Significant Word Register CAM15 Most Significant Word Register CAM15 Least Significant Word Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 117 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 CAMxM 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 MAC Address Byte 5 (MSB) MAC Address Byte 4 MAC Address Byte 3 MAC Address Byte 2 BITS DESCRIPTIONS [31:0] CAMxM The CAMxM(CAMx Most Significant Word) keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address. For example, if the MAC address 00-50-BA-33-BA-44 is kept in CAM entry 1, the register CAM1M is 32'h0050_BA33 and CAM1L is 32'hBA44_0000. - 118 - W90P710 CAMxL 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 Reserved 3 Reserved 2 1 0 26 18 10 25 17 9 24 16 8 MAC Address Byte 1 MAC Address Byte 0 (LSB) BITS DESCRIPTIONS [31:16] CAMxL The CAMxL(CAMx Least Significant Word) keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address. For example, if the MAC address 00-50-BA-33-BA-44 is kept in CAM entry 1, the register CAM1M is 32'h0050_BA33 and CAM1L is 32'hBA44_0000. - [15:0] Reserved CAM15M 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 OP-Code 26 18 10 2 25 17 9 1 24 16 8 0 Length/Type (MSB) Length/Type OP-Code (MSB) - 119 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS Length/Type Field of PAUSE Control Frame [31:0] Length/Type In the PAUSE control frame, a length/type field is defined and will be 16'h8808. OP Code Field of PAUSE Control Frame [15:0] OP-Code In the PAUSE control frame, an op code field is defined and will be 16'h0001. CAM15L 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 Operand 11 Reserved 3 Reserved 2 1 0 10 9 8 26 18 25 17 24 16 Operand (MSB) BITS DESCRIPTIONS [31:16] Operand Pause Parameter, In the PAUSE control frame, an operand field is defined and controls how much time the destination Ethernet MAC Controller is paused. The unit of the operand is the slot time, the 512 bits time. Reserved [15:0] - 120 - W90P710 Transmit Descriptor Link List Start Address Register (TXDLSA) The Tx descriptor defined in EMC is a link-list data structure. The TXDLSA keeps the starting address of this link-list. In other words, the TXDLSA keeps the starting address of the 1st Tx descriptor. S/W must configure TXDLSA before enable bit TXON of MCMDR register. Register TXDLSA Address 0xFFF0_3088 R/W R/W Description Transmit Descriptor Link List Start Address Register Reset Value 0xFFFF_FFFC 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 TXDLSA 19 TXDLSA 11 TXDLSA 3 TXDLSA 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] TXDLSA The TXDLSA(Transmit Descriptor Link-List Start Address) keeps the start address of transmit descriptor link-list. If the S/W enables the bit TXON of MCMDR register, the content of TXDLSA will be loaded into the current transmit descriptor start address register (CTXDSA). The TXDLSA doesn't be updated by EMC. During the operation, EMC will ignore the bits [1:0] of TXDLSA. This means that each Tx descriptor always must locate at word boundary memory address. Receive Descriptor Link List Start Address Register (RXDLSA) The Rx descriptor defined in EMC is a link-list data structure. The RXDLSA keeps the starting address of this link-list. In other words, the RXDLSA keeps the starting address of the 1st Rx descriptor. S/W must configure RXDLSA before enable bit RXON of MCMDR register. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RXDLSA 0xFFF0_308C R/W Receive Descriptor Link List Start Address Register 0xFFFF_FFFC - 121 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 RXDLSA RXDLSA RXDLSA RXDLSA BITS DESCRIPTIONS [31:0] RXDLSA The RXDLSA(Receive Descriptor Link-List Start Address) keeps the start address of receive descriptor link-list. If the S/W enables the bit RXON of MCMDR register, the content of RXDLSA will be loaded into the current receive descriptor start address register (CRXDSA). The RXDLSA doesn't be updated by EMC. During the operation, EMC will ignore the bits [1:0] of RXDLSA. This means that each Rx descriptor always must locate at word boundary memory address. MAC Command Register (MCMDR) The MCMDR provides the control information for EMC. Some command settings affect both frame transmission and reception, such as bit FDUP, the full/half duplex mode selection, or bit OPMOD, the 100/10M bps mode selection. Some command settings control frame transmission and reception separately, likes bit TXON and RXON. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MCMDR 0xFFF0_3090 R/W MAC Command Register 0x0000_0000 31 23 Reserved 30 22 14 6 29 21 LBK 13 Reserved 5 SPCRC 28 Reserved 20 OPMOD 12 4 AEP 27 19 EnMDC 11 3 ACP 26 18 FDUP 10 2 ARP 25 17 EnSQE 9 NDEF 1 ALP 24 SWR 16 SDPZ 8 TXON 0 RXON 15 7 Reserved - 122 - W90P710 BITS DESCRIPTIONS [31:25] Reserved The SWR (Software Reset) implements a reset function to make the EMC return default state. The SWR is a self-clear bit. This means after the software reset finished, the SWR will be cleared automatically. Enable SWR can also reset all control and status registers, except for OPMOD bit of MCMDR register. The EMC re-initial is needed after the software reset completed. 1'b0: Software reset completed. 1'b1: Enable software reset. [24] SWR [23:22] Reserved The LBK (Internal Loop Back Select) enables the EMC operating on internal loop-back mode. If the LBK is enabled, the packet transmitted out will be loop-backed to Rx. If the EMC is operating on internal loop-back mode, it also means the EMC is operating on fullduplex mode and the value of FDUP of MCMDR register is ignored. Beside, the LBK doesn't be affected by SWR bit. 1'b0: The EMC operates in normal mode. 1'b1: The EMC operates in internal loop-back mode. The Operation Mode Select defines the EMC is operating on 10M or 100M bps mode. The OPMOD doesn't be affected by SWR bit. 1'b0: The EMC operates on 10Mbps mode. 1'b1: The EMC operates on 100Mbps mode. The Enable MDC Clock Generation controls the MDC clock generation for MII Management Interface. If the EnMDC is set to 1, the MDC clock generation is enabled. Otherwise, the MDC clock generation is disabled. Consequently, if S/W wants to access the registers of external PHY through MII Management Interface, the EnMDC must be set to high. 1'b0: Disable MDC clock generation. 1'b1: Enable MDC clock generation. The Full Duplex Mode Select controls that EMC is operating on full or half duplex mode. 1'b0: The EMC operates on half duplex mode. 1'b1: The EMC operates on full duplex mode. [21] LBK [20] OPMOD [19] EnMDC [18] FDUP - 123 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [17] EnSQE The Enable SQE Checking controls the enable of SQE checking. The SQE checking is only available while EMC is operating on 10M bps and half duplex mode. In other words, the EnSQE cannot affect EMC operation, if the EMC is operating on 100M bps or full duplex mode. 1'b0: Disable SQE checking while EMC is operating on 10Mbps and half duplex mode. 1'b1: Enable SQE checking while EMC is operating on 10Mbps and half duplex mode. The Send PAUSE Frame controls the PAUSE control frame transmission. If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set. Then, set SDPZ to 1 enables the PAUSE control frame transmission. [16] SDPZ The SDPZ is a self-clear bit. This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. It is recommended that only enables SPDZ while EMC is operating on full duplex mode. 1'b0: The PAUSE control frame transmission has completed. 1'b1: Enable EMC to transmit a PAUSE control frame out. [15:10] Reserved The No Defer controls the enable of deferral exceed counter. If NDEF is set to high, the deferral exceed counter is disabled. The NDEF is only useful while EMC is operating on half duplex mode. 1'b0: The deferral exceed counter is enabled. 1'b1: The deferral exceed counter is disabled. [9] NDEF - 124 - W90P710 Continued. BITS DESCRIPTIONS The Frame Transmission ON controls the normal packet transmission of EMC. If the TXON is set to high, the EMC starts the packet transmission process, including the Tx descriptor fetching, packet transmission and Tx descriptor modification. [8] TXON It is must to finish EMC initial sequence before enable TXON. Otherwise, the EMC operation is undefined. If the TXON is disabled during EMC is transmitting a packet out, the EMC stops the packet transmission process after the current packet transmission finished. 1'b0: The EMC stops packet transmission process. 1'b1: The EMC starts packet transmission process. [7:6] Reserved The Strip CRC Checksum controls if the length of incoming packet is calculated with 4 bytes CRC checksum. If the SPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. 1'b0: The 4 bytes CRC checksum is included in packet length calculation. 1'b1: The 4 bytes CRC checksum is excluded in packet length calculation. The Accept CRC Error Packet controls the EMC accepts or drops the CRC error packet. If the AEP is set to high, the incoming packet with CRC error will be received by EMC as a good packet. 1'b0: The CRC error packet will be dropped by EMC. 1'b1: The CRC error packet will be accepted by EMC. The Accept Control Packet controls the control frame reception. If the ACP is set to high, the EMC will accept the control frame. Otherwise, the control frame will be dropped. [3] ACP It is recommended that S/W only enable AEP while EMC is operating on full duplex mode. 1'b0: The control frame will be dropped by EMC. 1'b1: The control frame will be accepted by EMC. [5] SPCRC [4] AEP - 125 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS The Accept Runt Packet controls the runt packet, which length is less than 64 bytes, reception. If the ARP is set to high, the EMC will accept the runt packet. [2] ARP Otherwise, the runt packet will be dropped. 1'b0: The runt packet will be dropped by EMC. 1'b1: The runt packet will be accepted by EMC. The Accept Long Packet controls the long packet, which packet length is greater than 1518 bytes, reception. If the ALP is set to high, the EMC will accept the long packet. [1] ALP Otherwise, the long packet will be dropped. 1'b0: The long packet will be dropped by EMC. 1'b1: The long packet will be accepted by EMC. The Frame Reception ON controls the normal packet reception of EMC. If the RXON is set to high, the EMC starts the packet reception process, including the Rx descriptor fetching, packet reception and Rx descriptor modification. [0] RXON It is must to finish EMC initial sequence before enable RXON. Otherwise, the EMC operation is undefined. If the RXON is disabled during EMC is receiving an incoming packet, the EMC stops the packet reception process after the current packet reception finished. 1'b0: The EMC stops packet reception process. 1'b1: The EMC starts packet reception process. MII Management Data Register (MIID) The EMC provides MII management function to access the control and status registers of the external PHY. The MIID register is used to store the data that will be written into the registers of external PHY for write command or the data that is read from the registers of external PHY for read command. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MIID 0xFFF0_3094 R/W MII Management Data Register 0x0000_0000 - 126 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 MIIData 4 MIIData 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Reserved Reserved BITS DESCRIPTIONS [31:16] Reserved The MII Management Data is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command. [15:0] MIIData MII Management Control and Address Register (MIIDA) The EMC provides MII management function to access the control and status registers of the external PHY. The MIIDA register is used to keep the MII management command information, like the register address, external PHY address, MDC clocking rate, read/write etc. RESET VALUE REGISTER ADDRESS R/W DESCRIPTION MIIDA 0xFFF0_3098 R/W MII Management Register Control and Address 0x0090_0000 31 23 15 7 30 22 MDCCR 14 Reserved 6 Reserved 29 21 13 5 28 20 12 4 27 Reserved 19 MDCON 11 3 26 18 PreSP 10 PHYAD 2 PHYRAD 25 17 BUSY 9 1 24 16 Write 8 0 - 127 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:24] Reserved The MDC Clock Rating controls the MDC clock rating for MII Management I/F. Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum period for MDC shall be 400ns. In other words, the maximum frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus clock, the HCLK. Consequently, for different HCLKs the different ratios are required to generate appropriate MDC clock. The following table shows relationship between HCLK and MDC clock in different MDCCR configurations. The THCLK indicates the period of HCLK. The MDC Clock ON Always controls the MDC clock generation. If the MDCON is set to high, the MDC clock actives always. Otherwise, the MDC will only active while S/W issues a MII management command. 1'b0: The MDC clock will only active while S/W issues a MII management command. 1'b1: The MDC clock actives always. The Preamble Suppress controls the preamble field generation of MII management frame. If the PreSP is set to high, the preamble field generation of MII management frame is skipped. 1'b0: Preamble field generation of MII management frame is not skipped. 1'b1: Preamble field generation of MII management frame is skipped. The Busy Bit controls the enable of the MII management frame generation. If S/W wants to access registers of external PHY, it set BUSY to high and EMC generates the MII management frame to external PHY through MII Management I/F. [23:20] MDCCR [19] MDC [18] PreSP [17] BUSY The BUSY is a self-clear bit. This means the BUSY will be cleared automatically after the MII management command finished. 1'b0: The MII management has finished. 1'b1: Enable EMC to generate a MII management command to external PHY. The Write Command defines the MII management command is a read or write. 1'b0: The MII management command is a read command. 1'b1: The MII management command is a write command. [16] Write [15:13] Reserved - 128 - W90P710 Continued. BITS DESCRIPTIONS [12:8] [7:5] [4:0] PHYAD Reserved PHYRAD The PHY Address keeps the address to differentiate which external PHY is the target of the MII management command. The PHY Register Address keeps the address to indicate which register of external PHY is the target of the MII management command. MDCCR [23:20] MDC CLOCK PERIOD MDC CLOCK FREQUENCY 4'b0000 4'b0001 4'b0010 4'b0011 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 4'b1001 4'b1010 4'b1011 4'b1100 4'b1101 4'b1110 4'b1111 4 x THCLK 6 x THCLK 8 x THCLK 12 x THCLK 16 x THCLK 20 x THCLK 24 x THCLK 28 x THCLK 30 x THCLK 32 x THCLK 36 x THCLK 40 x THCLK 44 x THCLK 48 x THCLK 54 x THCLK 60 x THCLK HCLK/4 HCLK/6 HCLK/8 HCLK/12 HCLK/16 HCLK/20 HCLK/24 HCLK/28 HCLK/30 HCLK/32 HCLK/36 HCLK/40 HCLK/44 HCLK/48 HCLK/54 HCLK/60 MII Management Function Frame Format In IEEE Std. 802.3 clause 22.2.4, the MII management function is defined. The MII management function is used for the purpose of controlling the PHY and gathering status from the PHY. The MII management frame format is shown as follow. - 129 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Management frame fields PRE READ WRITE 1...1 1...1 ST 01 01 OP 10 01 PHYAD AAAAA AAAAA REGAD RRRRR RRRRR TA Z0 10 DATA DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD IDLE Z Z MII Management Function Configure Sequence READ WRITE 1. 2. 3. 4. 5. 6. 7. Set appropriate MDCCR. Set PHYAD and PHYRAD. Set Write to 1'b0 Set bit BUSY to 1'b1 to send a MII management frame out. Wait BUSY to become 1'b0. Read data from MIID register. Finish the read command. 1. 2. 3. 4. 5. 6. 7. Write data to MIID register Set appropriate MDCCR. Set PHYAD and PHYRAD. Set Write to 1'b1 Set bit BUSY to 1'b1 to send a MII management frame out. Wait BUSY to become 1'b0. Finish the write command. FIFO Threshold Control Register (FFTCR) The FFTCR defines the high and low threshold of internal FIFOs, including TxFIFO and RxFIFO. The threshold of internal FIFOs is related to EMC request generation and when the frame transmission starts. The FFTCR also defines the burst length of AHB bus cycle for system memory access. REGISTER ADDRESS R/W DESCRIPTION FIFO Threshold Control Register RESET VALUE FFTCR 0xFFF0_309C R/W 0x0000_0101 31 23 Reserved 15 7 30 22 14 6 29 21 BLength 13 Reserved 5 Reserved 28 20 12 4 27 19 11 3 26 18 10 2 25 17 Reserved 9 TxTHD 1 RxTHD 24 16 8 0 Reserved - 130 - W90P710 BITS DESCRIPTIONS [31:22] Reserved The DMA Burst Length defines the burst length of AHB bus cycle while EMC accesses system memory. 2'b00: 4 words 2'b01: 8 words 2'b10: 16 words 2'b11: 16 words The TxFIFO Low Threshold controls when TxDMA requests internal arbiter for data transfer between system memory and TxFIFO. The TxTHD defines not only the low threshold of TxFIFO, but also the high threshold. The high threshold is the twice of low threshold always. During the packet transmission, if the TxFIFO reaches the high threshold, the TxDMA stops generate request to transfer frame data from system memory to TxFIFO. If the frame data in TxFIFO is less than low threshold, TxDMA starts to transfer frame data from system memory to TxFIFO. The TxTHD also defines when the TxMAC starts to transmit frame out to network. The TxMAC starts to transmit the frame out while the TxFIFO first time reaches the high threshold during the transmission of the frame. If the frame data length is less than TxFIFO high threshold, the TxMAC starts to transmit the frame out after the frame data are all inside the TxFIFO. 2'b00: Undefined. 2'b01: TxFIFO low threshold is 64B and high threshold is 128B. 2'b10: TxFIFO low threshold is 80B and high threshold is 160B. 2'b11: TxFIFO low threshold is 96B and high threshold is 192B. Reserved The RxFIFO High Threshold controls when RxDMA requests internal arbiter for data transfer between RxFIFO and system memory. The RxTHD defines not only the high threshold of RxFIFO, but also the low threshold. The low threshold is the half of high threshold always. During the packet reception, if the RxFIFO reaches the high threshold, the RxDMA starts to transfer frame data from RxFIFO to system memory. If the frame data in RxFIFO is less than low threshold, RxDMA stops to transfer the frame data to system memory. 2'b00: Depend on the burst length setting. If the burst length is 8 words, high threshold is 8 words, too. 2'b01: RxFIFO high threshold is 64B and low threshold is 32B. 2'b10: RxFIFO high threshold is 128B and low threshold is 64B. 2'b11: RxFIFO high threshold is 192B and low threshold is 96B. [21:20] Blength [19:10] Reserved [9:8] TxTHD [7:2] [1:0] RxTHD - 131 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Transmit Start Demand Register (TSDR) If the Tx descriptor is not available for use of TxDMA after the TXON of MCMDR register is enabled, the FSM (Finite State Machine) of TxDMA enters the Halt state and the frame transmission is halted. After the S/W has prepared the new Tx descriptor for frame transmission, it must issue a write command to TSDR register to make TxDMA leave Halt state and contiguous frame transmission. The TSDR is a write only register and read from this register is undefined. The write to TSDR register has took effect only while TxDMA stayed at Halt state. Register TSDR Address 0xFFF0_30A0 R/W W Description Transmit Start Demand Register Reset Value Undefined BITS DESCRIPTIONS [31:0] Reserved - Receive Start Demand Register (RSDR) If the Rx descriptor is not available for use of RxDMA after the RXON of MCMDR register is enabled, the FSM (Finite State Machine) of RxDMA enters the Halt state and the frame reception is halted. After the S/W has prepared the new Rx descriptor for frame reception, it must issue a write command to RSDR register to make RxDMA leave Halt state and contiguous frame reception. The RSDR is a write only register and read from this register is undefined. The write to RSDR register has took effect only while RxDMA stayed at Halt state. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RSDR 0xFFF0_30A4 W Receive Start Demand Register Undefined BITS DESCRIPTIONS [31:0] Reserved -- Maximum Receive Frame Control Register (DMARFC) The DMARFC defines the maximum frame length for a received frame that can be stored in the system memory. It is recommend that only use this register while S/W wants to receive a frame which length is greater than 1518 bytes. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE DMARFC 0xFFF0_30A8 R/W Maximum Register Receive Frame Control 0x0000_0800 - 132 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 RXMS 4 RXMS 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Reserved Reserved BITS DESCRIPTIONS [31:16] Reserved The Maximum Receive Frame Length defines the maximum frame length for received frame. If the frame length of received frame is greater than RXMS, and bit EnDFO of MIEN register is also enabled, the bit DFOI of MISTA register is set and the Rx interrupt is triggered. It is recommended that only use RXMS to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes. [15:0] RXMS MAC Interrupt Enable Register (MIEN) The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR for frame reception and TXINTR for frame transmission, are generated from EMC to CPU. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MIEN 0xFFF0_30AC R/W MAC Interrupt Enable Register 0x0000_0000 31 23 EnTDU 15 Reserved 7 EnMMP 30 22 EnLC 14 EnCFR 6 EnRP 29 21 EnTXABT 13 Reserved 5 EnALIE 28 Reserved 20 EnNCS 12 4 EnRXGD 27 19 EnEXDEF 11 EnRxBErr 3 EnPTLE 26 18 EnTXCP 10 EnRDU 2 EnRXOV 25 17 EnTXEMP 9 EnDEN 1 EnCRCE 24 EnTxBErr 16 EnTXINTR 8 EnDFO 0 EnRXINTR - 133 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:25] Reserved The Enable Transmit Bus Error Interrupt controls the TxBErr interrupt generation. If TxBErr of MISTA register is set, and both EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TxBErr of MISTA register is set. 1'b0: TxBErr of MISTA register is masked from Tx interrupt generation. 1'b1: TxBErr of MISTA register can participate in Tx interrupt generation. The Enable Transmit Descriptor Unavailable Interrupt controls the TDU interrupt generation. If TDU of MISTA register is set, and both EnTDU and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TDU of MISTA register is set. 1'b0: TDU of MISTA register is masked from Tx interrupt generation. 1'b1: TDU of MISTA register can participate in Tx interrupt generation. The Enable Late Collision Interrupt controls the LC interrupt generation. If LC of MISTA register is set, and both EnLC and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnLC or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the LC of MISTA register is set. 1'b0: LC of MISTA register is masked from Tx interrupt generation. 1'b1: LC of MISTA register can participate in Tx interrupt generation. The Enable Transmit Abort Interrupt controls the TXABT interrupt generation. If TXABT of MISTA register is set, and both EnTXABT and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXABT or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXABT of MISTA register is set. 1'b0: TXABT of MISTA register is masked from Tx interrupt generation. 1'b1: TXABT of MISTA register can participate in Tx interrupt generation. [24] EnTxBErr [23] EnTDU [22] EnLC [21] EnTXABT - 134 - W90P710 Continued. BITS DESCRIPTIONS [20] EnNCS The Enable No Carrier Sense Interrupt controls the NCS interrupt generation. If NCS of MISTA register is set, and both EnNCS and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnNCS or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the NCS of MISTA register is set. 1'b0: NCS of MISTA register is masked from Tx interrupt generation. 1'b1: NCS of MISTA register can participate in Tx interrupt generation. The Enable Defer Exceed Interrupt controls the EXDEF interrupt generation. If EXDEF of MISTA register is set, and both EnEXDEF and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnEXDEF or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the EXDEF of MISTA register is set. 1'b0: EXDEF of MISTA register is masked from Tx interrupt generation. 1'b1: EXDEF of MISTA register can participate in Tx interrupt generation. The Enable Transmit Completion Interrupt controls the TXCP interrupt generation. If TXCP of MISTA register is set, and both EnTXCP and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXCP or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXCP of MISTA register is set. 1'b0: TXCP of MISTA register is masked from Tx interrupt generation. 1'b1: TXCP of MISTA register can participate in Tx interrupt generation. The Enable Transmit FIFO Underflow Interrupt controls the TXEMP interrupt generation. If TXEMP of MISTA register is set, and both EnTXEMP and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXEMP or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXEMP of MISTA register is set. 1'b0: TXEMP of MISTA register is masked from Tx interrupt generation. 1'b1: TXEMP of MISTA register can participate in Tx interrupt generation. [19] EnEXDEF [18] EnTXCP [17] EnTXEMP - 135 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS The EnTXINTR controls the Tx interrupt generation. If Enable Transmit Interrupt is enabled and TXINTR of MISTA register is high, EMC generates the Tx interrupt to CPU. If EnTXINTR is disabled, no Tx interrupt is generated to CPU even the status bits 17~24 of MISTA are set and the corresponding bits of MIEN are enabled. In other words, if S/W wants to receive Tx interrupt from EMC, this bit must be enabled. And, if S/W doesn't want to receive any Tx interrupt from EMC, disables this bit. 1'b0: TXINTR of MISTA register is masked and Tx interrupt generation is disabled. 1'b1: TXINTR of MISTA register is unmasked and Tx interrupt generation is enabled. [15] Reserved -The Enable Control Frame Receive Interrupt controls the CFR interrupt generation. If CFR of MISTA register is set, and both EnCFR and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnCFR or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the CFR of MISTA register is set. 1'b0: CFR of MISTA register is masked from Rx interrupt generation. 1'b1: CFR of MISTA register can participate in Rx interrupt generation. [13:12] Reserved -The Enable Receive Bus Error Interrupt controls the RxBerr interrupt generation. If RxBErr of MISTA register is set, and both EnRxBErr and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRxBErr or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RxBErr of MISTA register is set. 1'b0: RxBErr of MISTA register is masked from Rx interrupt generation. 1'b1: RxBErr of MISTA register can participate in Rx interrupt generation. The Enable Receive Descriptor Unavailable Interrupt controls the RDU interrupt generation. If RDU of MISTA register is set, and both EnRDU and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRDU or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RDU of MISTA register is set. 1'b0: RDU of MISTA register is masked from Rx interrupt generation. 1'b1: RDU of MISTA register can participate in Rx interrupt generation. [16] EnTXINTR [14] EnCFR [11] EnRxBErr [10] EnRDU - 136 - W90P710 Continued. BITS DESCRIPTIONS [9] EnDEN The Enable DMA Early Notification Interrupt controls the DENI interrupt generation. If DENI of MISTA register is set, and both EnDEN and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the DENI of MISTA register is set. 1'b0: DENI of MISTA register is masked from Rx interrupt generation. 1'b1: DENI of MISTA register can participate in Rx interrupt generation. The Enable Maximum Frame Length Interrupt controls the DFOI interrupt generation. If DFOI of MISTA register is set, and both EnDFO and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnDFO or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the DFOI of MISTA register is set. 1'b0: DFOI of MISTA register is masked from Rx interrupt generation. 1'b1: DFOI of MISTA register can participate in Rx interrupt generation. [8] EnDFO [7] EnMMP The Enable More Missed Packet Interrupt controls the MMP interrupt generation. If MMP of MISTA register is set, and both EnMMP and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnMMP or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the MMP of MISTA register is set. 1'b0: MMP of MISTA register is masked from Rx interrupt generation. 1'b1: MMP of MISTA register can participate in Rx interrupt generation. [6] EnRP The Enable Runt Packet Interrupt controls the RP interrupt generation. If RP of MISTA register is set, and both EnRP and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRP or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RP of MISTA register is set. 1'b0: RP of MISTA register is masked from Rx interrupt generation. 1'b1: RP of MISTA register can participate in Rx interrupt generation. The Enable Alignment Error Interrupt controls the ALIE interrupt generation. If ALIE of MISTA register is set, and both EnALIE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnALIE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the ALIE of MISTA register is set. 1'b0: ALIE of MISTA register is masked from Rx interrupt generation. 1'b1: ALIE of MISTA register can participate in Rx interrupt generation. [5] EnALIE - 137 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [4] EnRXGD The Enable Receive Good Interrupt controls the RXGD interrupt generation. If RXGD of MISTA register is set, and both EnRXGD and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRXGD or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RXGD of MISTA register is set. 1'b0: RXGD of MISTA register is masked from Rx interrupt generation. 1'b1: RXGD of MISTA register can participate in Rx interrupt generation. The Enable Packet Too Long Interrupt controls the PTLE interrupt generation. If PTLE of MISTA register is set, and both EnPTLE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnPTLE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the PTLE of MISTA register is set. 1'b0: PTLE of MISTA register is masked from Rx interrupt generation. 1'b1: PTLE of MISTA register can participate in Rx interrupt generation. [3] EnPTLE [2] EnRXOV The Enable Receive FIFO Overflow Interrupt controls the RXOV interrupt generation. If RXOV of MISTA register is set, and both EnRXOV and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRXOV or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RXOV of MISTA register is set. 1'b0: RXOV of MISTA register is masked from Rx interrupt generation. 1'b1: RXOV of MISTA register can participate in Rx interrupt generation. [1] EnCRCE The Enable CRC Error Interrupt controls the CRCE interrupt generation. If CRCE of MISTA register is set, and both EnCRCE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnCRCE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the CRCE of MISTA register is set. 1'b0: CRCE of MISTA register is masked from Rx interrupt generation. 1'b1: CRCE of MISTA register can participate in Rx interrupt generation. - 138 - W90P710 Continued. BITS DESCRIPTIONS The Enable Receive Interrupt controls the Rx interrupt generation. If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx interrupt is generated to CPU even the status bits 1~14 of MISTA are set and the corresponding bits of MIEN are enabled. In other words, if S/W wants to receive Rx interrupt from EMC, this bit must be enabled. And, if S/W doesn't want to receive any Rx interrupt from EMC, disables this bit. 1'b0: RXINTR of MISTA register is masked and Rx interrupt generation is disabled. 1'b1: RXINTR of MISTA register is unmasked and Rx interrupt generation is enabled. [0] EnRXINTR MAC Interrupt Status Register (MISTA) The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO status and also NATA processing status. The statuses kept in MISTA will trigger the reception or transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the status and also clears the interrupt. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register 0x0000_0000 31 23 TDU 15 Reserved 30 22 LC 14 CFR 6 RP 29 21 TXABT 13 5 ALIE 28 Reserved 20 NCS 12 4 RXGD 27 19 EXDEF 11 RxBErr 3 PTLE 26 18 TXCP 10 RDU 2 RXOV 25 17 TXEMP 9 DENI 1 CRCE 24 TxBErr 16 TXINTR 8 DFOI 0 RXINTR Reserved 7 MMP - 139 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:25] Reserved The Transmit Bus Error Interrupt high indicates the memory controller replies ERROR response while EMC access system memory through TxDMA during packet transmission process. Reset EMC is recommended while TxBErr status is high. [24] TxBErr If the TxBErr is high and EnTxBErr of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TxBErr status. 1'b0: No ERROR response is received. 1'b1: ERROR response is received. The Transmit Descriptor Unavailable Interrupt high indicates that there is no available Tx descriptor for packet transmission and TxDMA will stay at Halt state. Once, the TxDMA enters the Halt state, S/W must issues a write command to TSDR register to make TxDMA leave Halt state while new Tx descriptor is available. If the TDU is high and EnTDU of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TDU status. 1'b0: Tx descriptor is available. 1'b1: Tx descriptor is unavailable. The Late Collision Interrupt high indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. [23] TDU [22] LC If the LC is high and EnLC of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the LC status. 1'b0: No collision occurred in the outside of 64 bytes collision window. 1'b1: Collision occurred in the outside of 64 bytes collision window. - 140 - W90P710 Continued. BITS DESCRIPTIONS The Transmit Abort Interrupt high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMC is operating on half-duplex mode. [21] TXABT If the TXABT is high and EnTXABT of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXABT status. 1'b0: Packet doesn't incur 16 consecutive collisions during transmission. 1'b1: Packet incurred 16 consecutive collisions during transmission. The No Carrier Sense Interrupt high indicates the MII I/F signal CRS doesn't active at the start of or during the packet transmission. The NCS is only available while EMC is operating on half-duplex mode. [20] NCS If the NCS is high and EnNCS of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the NCS status. 1'b0: CRS signal actives correctly. 1'b1: CRS signal doesn't active at the start of or during the packet transmission. The Defer Exceed Interrupt high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NDEF of MCMDR is disabled, and EMC is operating on half-duplex mode. [19] EXDEF If the EXDEF is high and EnEXDEF of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the EXDEF status. 1'b0: Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). 1'b1: Frame waiting for transmission has 0.32768ms (100Mbps) or 3.2768ms (10Mbps). deferred over - 141 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS The Transmit Completion Interrupt indicates the packet transmission has completed correctly. [18] TXCP If the TXCP is high and EnTXCP of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXCP status. 1'b0: The packet transmission doesn't complete. 1'b1: The packet transmission has completed. The Transmit FIFO Underflow Interrupt high indicates the TxFIFO underflow occurred during packet transmission. While the TxFIFO underflow occurred, the EMC will retransmit the packet automatically without S/W intervention. If the TxFIFO underflow occurred often, it is recommended that modify TxFIFO threshold control, the TxTHD of FFTCR register, to higher level. If the TXEMP is high and EnTXEMP of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXEMP status. 1'b0: No TxFIFO underflow occurred during packet transmission. 1'b0: TxFIFO underflow occurred during packet transmission. The Transmit Interrupt indicates the Tx interrupt status. If TXINTR high and its corresponding enable bit, EnTXINTR of MISTA register, is also high indicates the EMC generates Tx interrupt to CPU. If TXINTR is high but EnTXINTR of MISTA is disabled, no Tx interrupt is generated. The TXINTR is logic OR result of the bits 17~24 in MISTA register do logic AND with the corresponding bits in MIEN register. In other words, if one of the bits 17~24 in MISTA register is high and its corresponding enable bit in MIEN register is also enabled, the TXINTR will be high. Because the TXINTR is a logic OR result, clears bits 17~24 of MISTA register makes TXINTR be cleared, too. 1'b0: No status of bits 17~24 in MISTA is set or no enable of bits 17~24 in MIEN is turned on. 1'b1: At least one status of bits 17~24 in MISTA is set and its corresponding enable bit is turned on. [15] Reserved [17] TXEMP [16] TXINTR - 142 - W90P710 Continued. BITS DESCRIPTIONS The Control Frame Receive Interrupt high indicates EMC receives a flow control frame. The CFR only available while EMC is operating on full duplex mode. [14] CFR If the CFR is high and EnCFR of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the CFR status. 1'b0: The EMC doesn't receive the flow control frame. 1'b1: The EMC receives a flow control frame. [13:12] Reserved The Receive Bus Error Interrupt high indicates the memory controller replies ERROR response while EMC access system memory through RxDMA during packet reception process. Reset EMC is recommended while RxBErr status is high. [11] RxBErr If the RxBErr is high and EnRxBErr of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RxBErr status. 1'b0: No ERROR response is received. 1'b1: ERROR response is received. The Receive Descriptor Unavailable Interrupt high indicates that there is no available Rx descriptor for packet reception and RxDMA will stay at Halt state. Once, the RxDMA enters the Halt state, S/W must issues a write command to RSDR register to make RxDMA leave Halt state while new Rx descriptor is available. If the RDU is high and EnRDU of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RDU status. 1'b0: Rx descriptor is available. 1'b1: Rx descriptor is unavailable. The DMA Early Notification Interrupt high indicates the EMC has received the Length/Type field of the incoming packet. [9] DENI If the DENI is high and EnDENI of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the DENI status. 1'b0: The Length/Type field of incoming packet has not received yet. 1'b1: The Length/Type field of incoming packet has received. [10] RDU - 143 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [8] DFOI The Maximum Frame Length Interrupt high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped. If the DFOI is high and EnDFO of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the DFOI status. 1'b0: The length of the incoming packet doesn't exceed the length limitation configured in DMARFC. 1'b1: The length of the incoming packet has exceeded the length limitation configured in DMARFC. The More Missed Packet Interrupt high indicates the MPCNT, Missed Packet Count, has overflow. If the MMP is high and EnMMP of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the MMP status. 1'b0: The MPCNT has not rolled over yet. 1'b1: The MPCNT has rolled over yet. Runt Packet Interrupt The RP high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped. If the ARP of MCMDR register is set, the short packet is regarded as a good packet and RP will not be set. If the RP is high and EnRP of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RP status. 1'b0: The incoming frame is not a short frame or S/W wants to receive a short frame. 1'b1: The incoming frame is a short frame and dropped. The Alignment Error Interrupt high indicates the length of the incoming frame is not a multiple of byte. [7] MMP [6] RP [5] ALIE If the ALIE is high and EnALIE of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the ALIE status. 1'b0: The frame length is a multiple of byte. 1'b1: The frame length is not a multiple of byte. - 144 - W90P710 Continued. BITS DESCRIPTIONS The Receive Good Interrupt high indicates the frame reception has completed. [4] RXGD If the RXGD is high and EnRXGD of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RXGD status. 1'b0: The frame reception has not complete yet. 1'b1: The frame reception has completed. The Packet Too Long Interrupt high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. If the ALP of MCMDR register is set, the long packet will be regarded as a good packet and PTLE will not be set. [3] PTLE If the PTLE is high and EnPTLE of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the PTLE status. 1'b0: The incoming frame is not a long frame or S/W wants to receive a long frame. 1'b1: The incoming frame is a long frame and dropped. The Receive FIFO Overflow Interrupt high indicates the RxFIFO overflow occurred during packet reception. While the RxFIFO overflow occurred, the EMC drops the current receiving packer. If the RxFIFO overflow occurred often, it is recommended that modify RxFIFO threshold control, the RxTHD of FFTCR register, to higher level. If the RXOV is high and EnRXOV of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RXOV status. 1'b0: No RxFIFO overflow occurred during packet reception. 1'b0: RxFIFO overflow occurred during packet reception. The CRC Error Interrupt high indicates the incoming packet incurred the CRC error and the packet is dropped. If the AEP of MCMDR register is set, the CRC error packet will be regarded as a good packet and CRCE will not be set. [1] CRCE If the CRCE is high and EnCRCE of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the CRCE status. 1'b0: The frame doesn't incur CRC error. 1'b1: The frame incurred CRC error. [2] RXOV - 145 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS The Receive Interrupt indicates the Rx interrupt status. If RXINTR high and its corresponding enable bit, EnRXINTR of MISTA register, is also high indicates the EMC generates Rx interrupt to CPU. If RXINTR is high but EnRXINTR of MISTA is disabled, no Rx interrupt is generated. The RXINTR is logic OR result of the bits 1~14 in MISTA register do logic AND with the corresponding bits in MIEN register. In other words, if one of the bits 1~14 in MISTA register is high and its corresponding enable bit in MIEN register is also enabled, the RXINTR will be high. Because the RXINTR is a logic OR result, clears bits 1~14 of MISTA register makes RXINTR be cleared, too. 1'b0: No status of bits 1~14 in MISTA is set or no enable of bits 1~14 in MIEN is turned on. 1'b1: At least one status of bits 1~14 in MISTA is set and its corresponding enable bit is turned on. [0] RXINTR MAC General Status Register (MGSTA) The MGSTA also keeps the statuses of EMC. But the statuses in the MGSTA will not trigger any interrupt. The MGSTA is a write clear register and write 1 to corresponding bit clears the status. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MGSTA 0xFFF0_30B4 R/W MAC General Status Register 0x0000_0000 31 23 15 7 30 22 14 Reserved 6 CCNT 29 21 13 5 28 20 12 4 27 Reserved 19 Reserved 11 TXHA 3 Reserved 26 18 10 SQE 2 RFFull 25 17 9 PAU 1 RXHA 24 16 8 DEF 0 CFR - 146 - W90P710 BITS DESCRIPTIONS [31:12] [11] Reserved TXHA The Transmission Halted high indicates the next normal packet transmission process will be halted because the bit TXON of MCMDR is disabled be S/W. 1'b0: Next normal packet transmission process will go on. 1'b1: Next normal packet transmission process will be halted. The Signal Quality Error high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. The SQE error check will only be done while both bit EnSQE of MCMDR is enabled and EMC is operating on 10Mbps half-duplex mode. 1'b0: No SQE error found at end of packet transmission. 1'b0: SQE error found at end of packet transmission. The Transmission Paused high indicates the next normal packet transmission process will be paused temporally because EMC received a PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to transmit a PAUSE control frame out. 1'b0: Next normal packet transmission process will go on. 1'b1: Next normal packet transmission process will be paused. The Deferred Transmission high indicates the packet transmission has deferred once. The DEF is only available while EMC is operating on halfduplex mode. 1'b0: Packet transmission doesn't defer. 1'b1: Packet transmission has deferred once. The Collision Count indicates the how many collision occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4'h0 and bit TXABT will be set to 1. The RxFIFO Full indicates the RxFIFO is full due to four 64-byte packets are kept in RxFIFO and the following incoming packet will be dropped. 1'b0: The RxFIFO is not full. 1'b1: The RxFIFO is full and the following incoming packet will be dropped. The Receive Halted high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W. 1'b0: Next normal packet reception process will go on. 1'b1: Next normal packet reception process will be halted. The Control Frame Received high indicates EMC receives a flow control frame. The CFR only available while EMC is operating on full duplex mode. 1'b0: The EMC doesn't receive the flow control frame. 1'b1: The EMC receives a flow control frame. [10] SQE [9] PAU [8] DEF [7:4] [3] [2] CCNT Reserved RFFull [1] RXHA [0] CFR - 147 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Missed Packet Count Register (MPCNT) The MPCNT keeps the number of packets that were dropped due to various types of receive errors. The MPCNT is a read clear register. In addition, S/W also can write an initial value to MPCNT and the missed packet counter will start counting from that initial value. If the missed packet counter is overflow, the MMP of MISTA will be set. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MPCNT 0xFFF0_30B8 R/W Missed Packet Count Register 0x0000_7FFF 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 MPC 4 MPC 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Reserved Reserved BITS DESCRIPTIONS [31:16] Reserved The Miss Packet Count indicates the number of packets that were dropped due to various types of receive errors. The following type of receiving error makes missed packet counter increase: [15:0] MPC Incoming packet is incurred RxFIFO overflow. Incoming packet is dropped due to RXON is disabled. Incoming packet is incurred CRC error. MAC Receive Pause Count Register (MRPC) The EMC of W90P710 supports the PAUSE control frame reception and recognition. If EMC received a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored in the MRPC register. The MRPC register will keep the same while Tx of EMC is pausing due to the PAUSE control frame is received. The MRPC is read only and write to this register has no effect. - 148 - W90P710 REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MRPC 0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 MRPC 4 MRPC 27 Reserved 19 Reserved 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] Reserved MRPC The MAC Receive Pause Count keeps the operand field of the PAUSE control frame. It indicates how many slot time (512 bit time) the Tx of EMC will be paused. MAC Receive Pause Current Count Register (MRPCC) The EMC of W90P710 supports the PAUSE control frame reception and recognition. If EMC received a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored into a down count timer. The MRPCC shows the current value of that down count timer for S/W to know how long the Tx of EMC will be paused. The MRPCC is read only and write to this register has no effect. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MRPCC 0xFFF0_30C0 R MAC Receive Pause Current Count Register 0x0000_0000 - 149 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 Reserved 19 Reserved 11 MRPCC 3 MRPCC 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] Reserved The MAC Receive Pause Current Count shows the current value of that down count timer. If a new PAUSE control frame is received before the timer count down to zero, the new operand of the PAUSE control frame will be stored into the down count timer and the timer starts count down from the new value. [15:0] MRPCC MAC Remote Pause Count Register (MREPC) The EMC of W90P710 supports the PAUSE control frame transmission. After the PAUSE control frame is transmitted out completely, a timer starts to count down from the value of operand of the transmitted PAUSE control frame. The MREPC shows the current value of this down count timer. The MREPC is read only and write to this register has no effect. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MREPC 0xFFF0_30C4 R MAC Remote Pause Count Register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 Reserved 19 Reserved 11 MREPC 3 MREPC - 150 - 26 18 10 2 25 17 9 1 24 16 8 0 W90P710 BITS DESCRIPTIONS [31:16] [15:0] Reserved MREPC The MAC Remote Pause Count shows the current value of the down count timer that starts to count down from the value of operand of the transmitted PAUSE control frame. DMA Receive Frame Status Register (DMARFS) The DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. This register is writing clear and writes 1 to corresponding bit clears the bit. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE DMARFS 0xFFF0_30C8 R/W DMA Receive Frame Status Register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 RXFLT 4 RXFLT 27 Reserved 19 Reserved 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] Reserved The Receive Frame Length/Type keeps the Length/Type field of each incoming Ethernet packet. If the bit EnDEN of MIEN is enabled and the Length/Type field of incoming packet has received, the bit DENI of MISTA will be set and trigger interrupt. And, the content of Length/Type field will be stored in RXFLT. [15:0] RXFLT - 151 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Current Transmit Descriptor Start Address Register (CTXDSA) The CTXDSA keeps the start address of Tx descriptor that is used by TxDMA currently. The CTXDSA is read only and write to this register has no effect. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CTXDSA 31 23 15 7 0xFFF0_30C C 30 22 14 6 29 21 13 5 R Current Transmit Address Register 28 20 12 4 27 CTXDSA 19 CTXDSA 11 CTXDSA 3 CTXDSA Descriptor Start 0x0000_0000 24 16 8 0 26 18 10 2 25 17 9 1 BITS DESCRIPTIONS [31:0] CTXDSA Current Transmit Descriptor Start Address Current Transmit Buffer Start Address Register (CTXBSA) The CTXDSA keeps the start address of Tx frame buffer that is used by TxDMA currently. The CTXBSA is read only and write to this register has no effect. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CTXBSA 31 23 15 7 0xFFF0_30D0 30 22 14 6 29 21 13 5 R Current Transmit Address Register 28 20 12 4 CTXBSA 27 19 11 3 Buffer Start 0x0000_0000 24 16 8 0 26 18 10 2 25 17 9 1 CTXBSA CTXBSA CTXBSA - 152 - W90P710 BITS DESCRIPTIONS [31:0] CTXBSA Current Transmit Buffer Start Address Current Receive Descriptor Start Address Register (CRXDSA) The CRXDSA keeps the start address of Rx descriptor that is used by RxDMA currently. The CRXDSA is read only and write to this register has no effect. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CRXDSA 0xFFF0_30D4 R Current Receive Address Register Descriptor Start 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 CRXDSA 20 CRXDSA 12 CRXDSA 4 CRXDSA 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] CRXDSA Current Receive Descriptor Start Address Current Receive Buffer Start Address Register (CRXBSA) The CRXBSA keeps the start address of Rx frame buffer that is used by RxDMA currently. The CRXBSA is read only and write to this register has no effect. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CRXBSA 0xFFF0_30D8 R Current Receive Buffer Start Address Register 0x0000_0000 - 153 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 CRXBSA 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 CRXBSA CRXBSA CRXBSA BITS DESCRIPTIONS [31:0] CRXBSA Current Receive Buffer Start Address Receive Finite State Machine Register (RXFSM) The RXFSM shows the current value of the FSM (Finite State Machine) of RxDMA and RxFIFO controller. The RXFSM is read only and write to it has no effect. The RXFSM is used only for debug. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RXFSM 31 23 RX_FSM 15 7 0xFFF0_3200 30 22 Reserved R 29 21 13 5 Receive Finite State Machine Register 28 RX_FSM 20 12 4 RFF_FSM 19 11 3 18 RxBuf_FSM 10 2 9 1 17 27 26 25 0x0081_1101 24 16 8 0 14 RXFetch_FSM 6 RXClose_FSM - 154 - W90P710 BITS DESCRIPTIONS [31:23] [22] [21:16] [15:12] [11:8] [7:0] RX_FSM Reserved RXBuf_FSM RXFetch_FSM RXClose_FSM RFF_FSM RxDMA FSM Receive Buffer FSM Receive Descriptor Fetch FSM Receive Descriptor Close FSM RxFIFO Controller FSM Transmit Finite State Machine Register (TXFSM) The TXFSM shows the current value of the FSM (Finite State Machine) of TxDMA and TxFIFO controller. The TXFSM is read only and write to it has no effect. The TXFSM is used only for debug. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TXFSM 0xFFF0_3204 R Transmit Register Finite State Machine 0x0101_1101 31 23 Reserved 15 7 30 22 14 6 Reserved 29 21 13 5 28 TX_FSM 20 12 4 27 19 11 3 26 18 TxBuf_FSM 10 2 TFF_FSM 25 17 9 1 24 16 8 0 TXFetch_FSM TXClose_FSM - 155 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:24] [23:22] [21:16] [15:12] [11:8] [7:5] [4:0] TX_FSM Reserved TXBuf_FSM TXFetch_FSM TXClose_FSM Reserved TFF_FSM TxDMA FSM Transmit Buffer FSM Transmit Descriptor Fetch FSM Transmit Descriptor Close FSM TxFIFO Controller FSM Finite State Machine Register 0 (FSM0) The FSM0 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM0 is read only and write to it has no effect. The FSM0 is used only for debug. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FSM0 31 23 15 0xFFF0_3208 30 22 14 6 29 R Finite State Machine Register 0 28 20 12 4 27 19 11 3 STA_FSM 26 18 10 TXDefer_FSM 2 25 17 9 1 0x0001_0101 24 TXMAC_FSM 16 8 0 Reserved 21 13 5 TXMAC_FSM Reserved 7 BITS DESCRIPTIONS [31:26] [25:16] [15:14] [13:8] [7:0] Reserved TXMAC_FSM Reserved TXDefer_FSM STA_FSM TxMAC FSM Transmit Defer Process FSM MII Management I/F FSM - 156 - W90P710 Finite State Machine Register 1 (FSM1) The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug. Register FSM1 Address 0xFFF0_320C R/W R Description Finite State Machine Register 1 Reset Value 0x1100_0100 31 Reserved 30 22 14 6 29 ARB_FSM 21 13 5 28 20 Reserved 12 4 Reserved 27 19 11 3 26 18 10 AHB_FSM 2 25 17 9 1 24 16 8 0 TxPause_FSM 23 15 Reserved 7 BITS DESCRIPTIONS [31] [30:28] [27:24] [23:14] [13:8] [7:0] Reserved ARB_FSM TxPause_FSM Reserved AHB_FSM RESERVED Internal Arbiter FSM Transmit PAUSE Control Frame FSM [13:8]: AHB Master FSM - Debug Configuration Register (DCR) The DCR is for debug only to multiplex different signal group out. In FPGA emulation, the signals are outputted to probe pins in emulation board. In real chip, the signals are outputted through the GPIO pins. Register DCR Address 0xFFF0_3210 R/W R/W Description Debug Configuration Register Reset Value 0x0000_003f - 157 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 Enable 15 7 Out 30 22 14 6 29 21 13 5 28 20 12 4 27 Reserved 26 18 Reserved 10 2 Config 25 17 9 1 24 16 8 0 19 11 3 Reserved BITS DESCRIPTIONS [31:24] Reserved The Function Enable outputs two function enable signals to external stimulus circuit. [23:22] Enable At this stage, only the bit 22 is used for external random collision generator. The random collision generator used only in FPGA emulation. The Flag Out provides two output flags to trigger Logic Analyzer for debug. These two bits can be written at any time. The Configuration controls which group of internal signals can be multiplexed out for debug. Each group includes 16 signals. [21:8] [7:6] [5:0] Reserved Out Config CONFIG SIGNALS CONFIG SIGNALS OUT [6], TransDone, GrantLost, 6'h00 Trans_CTR [4:0], LAST, TransCtrExpire, DMode_AHB_CS [5:0] 6'h02 OUT [6], DMode_RXBuf_CS [5:0], DMode_RXFSM_CS [8:0] TxBuf_DRDY, TFF_WPTR [5:0], TX_START, TXSTART, READ, TFF_RPTR [5:0] OUT [6], TXFIFO_HT, TXFIFO_LT, 6'h03 DMode_TFF_CS [4:0], DMode_RFF_CS [7:0] WRITE, RFF_WPTR [5:0], RXFIFO_HT, RXFIFO_LT, RxBuf_ACK, RFF_RPTR [5:0] 6'h01 OUT [6], DMode_TxBuf_CS [6:0] DMode_TXFSM_CS [7:0] 6'h04 6'h05 - 158 - W90P710 Continued. CONFIG SIGNALS CONFIG SIGNALS 6'h06 6'h08 R0_PTLE, RxStart, SFD, WasSFD, RxFrame, WrByte, Rx_OvFlow, 1'b0, R0_RBC [7:0] Reserved OUT [7:6], RegMISTA_Rx_W, RXERR_sync, R0_CRCE, R0_PTLE, R0_RP, RegMISTA_Tx_W, T0_EXDEF, T0_TXABT, T0_CCNT [3:0], 2'b00 OUT [7:6], FrameWPtr [1:0], FrameRPtr [1:0], RFF_One, FrameWPtr_Inc, FrameRPtr_Inc, Rounding, NexPktStartPtr [5:0] R0_CRCE, Rx_OvFlow, R0_MRE, CRCERR, DAMATCH, RxFrame, SFD, RxMIIErr, SynStart, Hi_Lo_Syn, New_DataValid, L_RxFrame, RxStart, DataValid, Hi_Lo, RX_DV_In WRITE, RFF_CS [7:1], RFF_WPTR [5:0], RXERR_sync, RxReuse OUT [6], TXSTART, TX_START, DMode_TFF_CS [4:0], TXSTART_Set, TXSTART_Clr, TXSTART_Re_Set, FrameWaiting, Deferring, COL, TXCOL, TXCOL_sync OUT [6], READ, READ_sync, READ_Mask, ReadMask_sync, TFF_RPTR [5:0], DMode_TFF_CS [4:0] 6'h07 6'h09 6'h0A 6'h0B 6'h0C 6'h0D R0_CRCE, RX_DV_In, SynStart, R0_DB, Rx_OvFlow, WRITECTR [2:0], RxByte [7:0] Reserved OUT [7:6], MCMDR_SDPZ_Clr, RegMCMDR_SDPZ_Clr, DMode_Pause_CS [3:0], MacCtlFra, PauseFra, PauseTx, MacCtlFra_sync, PauseFra_sync, PAUSE, Pause_en, FDUP OUT [7:6], ARB_REQ_Set, ARB_REQ_Clr, DMode_ARB_CS [2:0], TransDone, GrantLost, TransCtrExpire, Trans_CTR [4:0], BURST 6'h0E 6'h0F OUT [6], WRITE, RFF_WPTR [5:0], RxReuse, RxBuf_ACK, RFF_RPTR [5:0] 6'h10 6'h11 OUT [6], TX_CLK, TX_EN, TXD [3:0], RX_CLK, RX_DV, RX_ER, RXD [3:0], CRS, COL 6'h12 6'h13 OUT [6], DMode_TxBuf_CS[6:0], DMode_TFF_CS[4:0], TXFIFO_UF, TXFIFO_HT, TXOK_sync 6'h14 6'h15 - 159 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Debug Mode MAC Information Register (DMMIR) The DMMIR keeps the information of MAC module for debug. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE DMMIR 0xFFF0_3214 R Debug Mode MAC Information Register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 RBC 4 RBC 27 Reserved 26 18 10 2 25 17 9 1 24 16 8 0 19 11 3 Reserved BITS DESCRIPTIONS [31:16] [15:0] Reserved RBC Receive Byte Count BIST Mode Register (BISTR) The BISTR controls the BIST (Built In Self Test) for embedded SRAM, 256B for RxFIFO and 256B for TxFIFO. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE BISTR 0xFFF0_3300 R/W BIST Mode Register 0x0000_0000 31 23 15 7 30 22 14 29 21 13 28 20 12 4 27 Reserved 26 18 10 2 BistFail 25 17 9 1 Finish 24 16 8 0 BMEn 19 Reserved 11 Reserved 3 6 5 Reserved - 160 - W90P710 BITS DESCRIPTIONS [31:5] Reserved The BIST Fail indicates if the BIST test fails or succeeds. If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation. If BistFail[2] high indicates the embedded SRAM for TxFIFO BIST test failed. If BistFail[3] high indicates the embedded SRAM for RxFIFO BIST test failed. The BistFail is a write clear field. Write 1 to this field clears the content and write 0 has no effect. The BIST Operation Finish indicates the end of the BIST operation. When BIST controller finishes all operations, this bit will be high. The Finish is a write clear field. Write 1 to this field clears the content and write 0 has no effect. The BIST Mode Enable is used to enable the BIST operation. If high enables the BIST controller to do embedded SRAM test. This bit is also used to do the reset for BIST circuit. It is necessary to reset the BIST circuit one clock cycle at least in order to initialize the BIST properly. The BMEn can be disabled by write 0. [3:2] BistFail [1] Finish [0] BMEn - 161 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.6 GDMA Controller The W90P710 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs the following data transfers without the CPU intervention: Memory-to-memory (memory to/from memory) Memory -to - IO IO- to -memory The on-chip GDMA can be started by the software or external DMA request nXDREQ. Software can also be used to restart the GDMA operation after it has been stopped. The CPU can recognize the completion of a GDMA operation by software polling or when it receives an internal GDMA interrupt. The W90P710 GDMA controller can increment source or destination address, decrement them as well, and conduct 8bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. The GDMA includes the following features AMBA AHB compliant Supports 4-data burst mode to boost performance Provides support for external GDMA device Demand mode speeds up external GDMA operations 7.6.1 GDMA Functional Description The GDMA directly transfers data between source and destination. The GDMA starts to transfer data after it receives service requests from nXDREQ signal or software. When the entire data have been transferred completely, the GDMA becomes idle. Nevertheless, if another transfer is needed, then the GDMA must be programmed again. There are three transfer modes: Single Mode Single mode requires a GDMA request for each data transfer. A GDMA request (nXDREQ or software) causes one byte, one half-word, or one word to transfer if the 4-data burst mode is disabled, or four times of transfer width is the 4-data burst mode is enabled. Block Mode The assertion of a single GDMA request causes all of the data to be transferred in a single operation. The GDMA transfer is completed when the current transfer count register reaches zero. Demand Mode The GDMA continues transferring data until the GDMA request input nXDREQ becomes inactive. - 162 - W90P710 7.6.2 GDMA Register Map ADDRESS R/W DESCRIPTION RESET VALUE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER Channel 0 GDMA_CTL0 GDMA_SRCB0 GDMA_DSTB0 GDMA_TCNT0 GDMA_CSRC0 GDMA_CDST0 0xFFF0_4000 0xFFF0_4004 0xFFF0_4008 0xFFF0_400C 0xFFF0_4010 0xFFF0_4014 R/W Channel 0 Control Register R/W Channel 0 Source Base Address Register R/W Channel 0 Destination Base Address Register R/W Channel 0 Transfer Count Register R R R Channel 0 Current Source Address Register Channel 0 Current Destination Address Register Channel 0 Current Transfer Count Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 GDMA_CTCNT0 0xFFF0_4018 Channel 1 GDMA_CTL1 GDMA_SRCB1 GDMA_DSTB1 GDMA_TCNT1 GDMA_CSRC1 GDMA_CDST1 0xFFF0_4020 0xFFF0_4024 0xFFF0_4028 0xFFF0_402C 0xFFF0_4030 0xFFF0_4034 R/W Channel 1 Control Register R/W Channel 1 Source Base Address Register R/W Channel 1 Destination Base Address Register R/W Channel 1 Transfer Count Register R R R Channel 1 Current Source Address Register Channel 1 Current Destination Address Register Channel 1 Current Transfer Count Register GDMA_CTCNT1 0xFFF0_4038 Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1) REGISTER ADDRESS R/W DESCRIPTION Channel 0 Control Register Channel 1 Control Register RESET VALUE GDMA_CTL0 GDMA_CTL1 0xFFF0_4000 0xFFF0_4020 R/W R/W 0x0000_0000 0x0000_0000 31 RESERVED 30 22 SABNDERR 29 TC_WIDTH 28 20 12 TWS 23 RW_TC 21 13 5 SADIR 27 26 REQ_SEL 19 18 TC 25 REQ_ATV 24 ACK_ATV 17 BLOCK 16 SOFTREQ DABNDERR GDMAERR AUTOIEN 15 DM 14 RESERVED 11 SBMS 10 RESERVED 9 BME 8 SIEN 7 SAFIX 6 DAFIX 4 DADIR 3 GDMAMS 2 1 RESERVED 0 GDMAEN - 163 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31] [30:28] RESERVED TC_WIDTH nRTC/nWTC active width selection, from 1 to 7 HCLK cycles. External request pin selection, if GDMAMS [3:2]=00, REQ_SEL will be don't care. If REQ_SEL [27:26]=00, external request don't use. If REQ_SEL [27:26]=01, use nXDREQ. If REQ_SEL [27:26]=10, external request don't use. If REQ_SEL [27:26]=11, external request don't use. nXDREQ High/Low active selection 1'b0 = nXDREQ is LOW active. 1'b1 = nXDREQ is HIGH active. nXDACK High/Low active selection 1'b0 = nXDACK is LOW active. 1'b1 = nXDACK is HIGH active. Read/Write terminal count output selection. 1'b0 = output to nRTC. 1'b1 = output to nWTC. Source address Boundary alignment Error flag If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00 If TWS [13:12]=01, GDMA_SRCB [0] should be 0 The address boundary alignment should be depended on TWS [13:12]. 1'b0 = the GDMA_SRCB is on the boundary alignment. 1'b1 = the GDMA_SRCB not on the boundary alignment The SABNDERR register bits just can be read only. Destination address Boundary alignment Error flag If TWS [13:12]=10, GDMA_DSTB [1:0] should be 00 If TWS [13:12]=01, GDMA_DSTB [0] should be 0 The address boundary alignment should be depended on TWS [13:12]. 1'b0 = the GDMA_DSTB is on the boundary alignment. 1'b1 = the GDMA_DSTB not on the boundary alignment The DABNDERR register bits just can be read only. GDMA Transfer Error 1'b0 = No error occurs 1'b1 = Hardware sets this bit on a GDMA transfer failure Transfer error will generate GDMA interrupt [27:26] REQ_SEL [25] REQ_ATV [24] ACK_ATV [23] RW_TC [22] SABNDERR [21] DABNDERR [20] GDMATERR - 164 - W90P710 Continued BITS DESCRIPTIONS [19] AUTOIEN Auto initialization Enable 1'b0 = Disables auto initialization 1'b1 = Enables auto initialization, the GDMA_CSRC0/1, GDMA_CDST0/1,and GDMA_CTCNT0/1 registers are updated by the GDMA_SRC0/1,GDMA_DST0/1,and GDMA_TCNT0/1 registers automatically when transfer is complete. Terminal Count 1'b0 = Channel does not expire 1'b1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 0. TC [18] is the GDMA interrupt flag. TC [18] or GDMATERR[20] will generate interrupt Bus Lock 1'b0 = Unlocks the bus during the period of transfer 1'b1 = Locks the bus during the period of transfer Software Triggered GDMA Request Software can request the GDMA transfer service by setting this bit to 1. This bit is automatically cleared by hardware when the transfer is completed. This bit is available only while GDMAMS [3:2] register bits are set on software mode (memory to memory). Demand Mode 1'b0 = Normal external GDMA mode 1'b1 = When this bit is set to 1, the external GDMA operation is speeded up. When external GDMA device is operating in the demand mode, the GDMA transfers data as long as the external GDMA request signal nXDREQ is active. The amount of data transferred depends on how long the nXDREQ is active. When the nXDREQ is active and GDMA gets the bus in Demand mode, DMA holds the system bus until the nXDREQ signal becomes non-active. Therefore, the period of the active nXDREQ signal should be carefully tuned such that the entire operation does not exceed an acceptable interval (for example, in a DRAM refresh operation). - [18] TC [17] BLOCK [16] SOFTREQ [15] DM [14] Reserved - 165 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS [13:12] TWS Transfer Width Select 00 = One byte (8 bits) is transferred for every GDMA operation 01 = One half-word (16 bits) is transferred for every GDMA operation 10 = One word (32 bits) is transferred for every GDMA operation 11 = Reserved The GDMA_SCRB and GDMA_DSTB should be alignment under the TWS selection Single/Block Mode Select 1'b0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation. 1'b1 = Selects block mode. It requires a single external GDMA request during the atomic GDMA operation. An atomic GDMA operation is defined as the sequence of GDMA operations until the transfer count register reaches zero. Burst Mode Enable 1'b0 = Disables the 4-data burst mode 1'b1 = Enables the 4-data burst mode FF there are 16 words to be transferred, and BME [9]=1, the GDMA_TCNT should be 0x04; However, if BME [9]=0, the GDMA_TCNT should be 0x10. Stop Interrupt Enable 1'b0 = Do not generate an interrupt when the GDMA operation is stopped 1'b1 = Interrupt is generated when the GDMA operation is stopped Source Address Fixed 1'b0 = Source address is changed during the GDMA operation 1'b1 = Do not change the destination address during the GDMA operation. This feature can be used when data were transferred from a single source to multiple destinations. Destination Address Fixed 1'b0 = Destination address is changed during the GDMA operation 1'b1 = Do not change the destination address during the GDMA operation. This feature can be used when data were transferred from multiple sources to a single destination. Source Address Direction 1'b0 = Source address is incremented successively 1'b1 = Source address is decremented successively [11] SBMS [10] Reserved [9] BME [8] SIEN [7] SAFIX [6] DAFIX [5] SADIR - 166 - W90P710 Continued BITS DESCRIPTIONS [4] DADIR Destination Address Direction 1'b0 = Destination address is incremented successively 1'b1 = Destination address is decremented successively GDMA Mode Select 00 = Software mode (memory-to-memory) 01 = External nXDREQ mode for external device 10 = Reserved 11 = Reserved GDMA Enable 1'b0 = Disables the GDMA operation 1'b1 = Enables the GDMA operation; this bit will be clear automatically when the transfer is complete on AUTOIEN [19] register bit is on Disable mode. [3:2] GDMAMS [1] Reserved [0] GDMAEN Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1) The GDMA channel starts reading its data from the source address as defined in this source base address register. REGISTER ADDRESS R/W DESCRIPTION Channel 0 Source Base Address Register Channel 1 Source Base Address Register RESET VALUE GDMA_SRCB0 GDMA_SRCB1 31 23 15 7 0xFFF0_4004 0xFFF0_4024 30 22 14 6 29 21 13 5 R/W R/W 0x0000_0000 0x0000_0000 25 17 9 1 24 16 8 0 28 27 SRC_BASE_ADDR [31:24] 20 19 SRC_BASE_ADDR [23:16] 12 11 SRC_BASE_ADDR [15:8] 4 3 SRC_BASE_ADDR [7:0] DESCRIPTIONS 26 18 10 2 BITS [31:0] SRC_BASE_ADDR 32-bit Source Base Address - 167 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA_DSTB1) Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1) The GDMA channel starts writing its data to the destination address as defined in this destination base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address. REGISTER ADDRESS R/W DESCRIPTION Channel 0 Destination Base Address Register Channel 1 Destination Base Address Register RESET VALUE GDMA_DSTB0 GDMA_DSTB1 31 23 15 7 0xFFF0_4008 0xFFF0_4028 30 22 14 6 29 21 13 5 R/W R/W 0x0000_0000 0x0000_0000 25 17 9 1 24 16 8 0 28 27 DST_BASE_ADDR [31:24] 20 19 DST_BASE_ADDR [23:16] 12 11 DST_BASE_ADDR [15:8] 4 3 DST_BASE_ADDR [7:0] DESCRIPTIONS 26 18 10 2 BITS [31:0] DST_BASE_ADDR 32-bit Destination Base Address Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) REGISTER ADDRESS R/W DESCRIPTION Channel 0 Transfer Count Register Channel 1 Transfer Count Register RESET VALUE GDMA_TCNT0 GDMA_TCNT1 31 23 15 7 0xFFF0_400C 0xFFF0_402C 30 22 14 6 29 21 13 5 R/W R/W 0x0000_0000 0x0000_0000 25 17 9 1 24 16 8 0 28 27 Reserved 20 19 TFR_CNT [23:16] 12 11 TFR_CNT [15:8] 4 3 TFR_CNT [7:0] 26 18 10 2 - 168 - W90P710 BITS DESCRIPTIONS [31:24] [23:0] Reserved TFR_CNT The TFR_CNT represents the required number of GDMA transfers. The maximum transfer count is 16M -1. Channel 0/1 Current Source Register (GDMA_CSRC0, GDMA_CSRC1) REGISTER ADDRESS R/W DESCRIPTION Channel 0 Current Source Address Register Channel 1 Current Source Address Register RESET VALUE GDMA_CSRC0 GDMA_CSRC1 0xFFF0_4010 0xFFF0_4030 R R 0x0000_0000 0x0000_0000 31 23 15 7 30 22 14 6 29 28 27 CURRENT_SRC_ADDR [31:24] 21 20 19 CURRENT_SRC_ADDR [23:16] 13 12 11 CURRENT_SRC_ADDR [15:8] 5 4 3 CURRENT_SRC_ADDR [7:0] 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] CURRENT_SRC_ADDR The 32-bit Current Source Address indicates the source address where the GDMA transfer is just occurring. During a block transfer, the GDMA determines the successive source addresses by adding to or subtracting from the source base address. Depending on the settings you make to the control register, the current source address will remain the same or will be incremented or decremented. - 169 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GDMA_CDST0 GDMA_CDST1 0xFFF0_4014 0xFFF0_4034 R R Channel 0 Current Destination Address Register Channel 1 Current Destination Address Register 0x0000_0000 0x0000_0000 31 23 15 7 30 22 14 6 28 27 CURRENT_DST_ADDR [31:24] 21 20 19 CURRENT_DST_ADDR [23:16] 13 12 11 CURRENT_DST_ADDR [15:8] 5 4 3 CURRENT_DST_ADDR [7:0] 29 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] CURRENT_DST_ADDR The 32-bit Current Destination Address indicates the destination address where the GDMA transfer is just occurring. During a block transfer, the GDMA determines the successive destination addresses by adding to or subtracting from the destination base address. Depending on the settings you make to the control register, the current destination address will remain the same or will be incremented or decremented. Channel 0/1 Current Transfer Count Register (GDMA_CTCNT0, GDMA_CTCNT1) The Current transfer count register indicates the number of transfer being performed. REGISTER ADDRESS R/W DESCRIPTION Channel 0 Current Transfer Count Register Channel 1 Current Transfer Count Register RESET VALUE GDMA_CTCNT0 GDMA_CTCNT1 0xFFF0_4018 0xFFF0_4038 R R 0x0000_0000 0x0000_0000 - 170 - W90P710 31 23 15 7 30 22 14 6 29 21 28 Reserved 27 26 18 10 2 25 17 9 1 24 16 8 0 20 19 CURENT_TFR_CNT [23:16] 13 12 11 CURRENT_TFR_CNT [15:8] 5 4 3 CURRENT_TFR_CNT [7:0] BITS DESCRIPTIONS [31:24] Reserved Current Transfer Count register [23:0] CURRENT_TFR_CNT The current transfer count register indicates the number of transfer being performed - 171 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.7 USB Host Controller The Universal Serial Bus (USB) is a low-cost, low-to-mid-speed peripheral interface standard intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a highbandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a network of peripheral devices. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. Peripherals may be attached, configured, used, and detached, while the host and other peripherals continue operation (i.e. hot plug and unplug is supported). A major design goal of the USB standard was to allow flexible, plug-and-play networks of USB devices. In any USB network, there will be only one host, but there can be many devices and hubs. The USB Host Controller has the following features: * Open Host Controller Interface (OHCI) Revision 1.0 compatible. * USB Revision 1.1 compatible * Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices. * Handles all the USB protocol. * Built-in DMA for real-time data transfer * Multiple low power modes for efficient power management 7.7.1 USB Host Functional Description 7.7.1.1. AHB Interface The OpenHCI Host Controller is connected to the system by the AHB bus. The design requires both master and slave bus operations. As a master, the Host Controller is responsible for running cycles on the AHB bus to access EDs and TDs as well as transferring data between memory and the local data buffer. As a slave, the Host Controller monitors the cycles on the AHB bus and determines when to respond to these cycles. Configuration and non-real-time control access to the Host Controller operational registers are through the AHB bus slave interface. 7.7.1.2. Host Controller List Processing The List Processor manages the data structures from the Host Controller Driver and coordinates all activity within the Host Controller. Frame Management Frame Management is responsible for managing the frame specific tasks required by the USB specification and the OpenHCI specification. These tasks are: 1) 2) 3) 4) Management of the OpenHCI frame specific Operational Registers Operation of the Largest Data Packet Counter. Performing frame qualifications on USB Transaction requests to the SIE. Generate SOF token requests to the SIE. - 172 - W90P710 Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific event sets a specific bit in the HcInterruptStatus register. Host Controller Bus Master The Host Controller Bus Master is the central block in the data path. The Host Controller Bus Master coordinates all access to the AHB Interface. There are two sources of bus mastering within Host Controller: the List Processor and the Data Buffer Engine. Data Buffer The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a combination of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword AHB Holding Register. 7.7.1.3. USB Interface The USB interface includes the integrated Root Hub with two external ports, Port 1 and Port 2 as well as the Serial Interface Engine (SIE) and USB clock generator. The interface combines responsibility for executing bus transactions requested by the HC as well as the hub and port management specified by USB. 7.7.2 USB Host Controller Registers Map REGISTER ADDRESS 0xFFF0_5000 R/W DESCRIPTION RESET VALUE OpenHCI Registers HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnbale HcInterruptDisbale HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadEd HcBulkCurrentED R Host Controller Revision Register 0x0000_0010 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF0_5004 R/W Host Controller Control Register 0xFFF0_5008 R/W Host Controller Command Status Register 0xFFF0_500C R/W Host Controller Interrupt Status Register 0xFFF0_5010 R/W Host Controller Interrupt Enable Register 0xFFF0_5014 R/W Host Controller Interrupt Disable Register 0xFFF0_5018 R/W 0xFFF0_501C R/W Host Controller Register Host Controller Register Host Controller Register Communication Period Current Area ED 0xFFF0_5020 R/W Host Controller Control Head ED Register 0xFFF0_5024 R/W Control Current ED 0xFFF0_5028 R/W Host Controller Bulk Head ED Register 0xFFF0_502C R/W Host Controller Bulk Current ED Register - 173 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OpenHCI Registers HcDoneHeadED HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus [1] HcRhPortStatus [2] 0xFFF0_5030 R/W Host Controller Done Head Register 0xFFF0_5034 R/W Host Controller Frame Interval Register 0xFFF0_5038 0xFFF0_503C 0x0000_0000 0x0000_2EDF 0x0000_0000 0x0000_0000 R R Host Controller Frame Remaining Register 0x0000_0000 Host Controller Frame Number Register 0xFFF0_5040 R/W Host Controller Periodic Start Register 0xFFF0_5044 R/W 0xFFF0_5048 R/W 0xFFF0_504C R/W Host Controller Low Speed Threshold 0x0000_0628 Register Host Controller Root Hub Descriptor A 0x0100_0002 Register Host Controller Root Hub Descriptor B 0x0000_0000 Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0XXX_XXXX 0x0000_0000 0xFFF0_5050 R/W Host Controller Root Hub Status Register 0xFFF0_5054 R/W Host Controller Root Hub Port Status [1] 0xFFF0_5058 R/W Host Controller Root Hub Port Status [2] 0xFFF0_5200 R/W USB Test Mode Enable Register USB Configuration Registers TestModeEnable OperationalModeEnable 0xFFF0_5204 R/W USB Operational Mode Enable Register - 174 - W90P710 Host Controller Revision Register REGISTER HcRevision OFFSET ADDRESS 0xFFF0_5000 R/W DESCRIPTION RESET VALUE R Host Controller Revision Register 28 27 Reserved 20 19 Reserved 12 11 Reserved 4 3 Revision 26 18 10 2 25 17 9 1 0x0000_0010 24 16 8 0 31 23 15 7 30 22 14 6 29 21 13 5 BITS DESCRIPTION [31:8] [7:0] Reserved Revision Reserved. Read/Write 0's Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.0 specification. (X.Y = XYh) Host Controller Control Register REGISTER HcControl ADDRESS 0xFFF0_5004 R/W DESCRIPTION RESET VALUE R/W Host Controller Control Register 28 27 26 18 10 RWCE 2 PLE 25 17 9 RWC 1 0x0000_0000 24 16 8 IR 0 CBR 31 23 15 7 HCFS 30 22 14 6 29 21 13 Reserved 5 BLE Reserved 20 19 Reserved 12 11 4 CLE 3 ISE - 175 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:11] [10] Reserved RWCE Reserved. Read/Write 0's RemoteWakeupConnectedEnable If a remote wakeup signal is supported, this bit enables that operation. Since there is no remote wakeup signal supported, this bit is ignored. RemoteWakeupConnected This bit indicated whether the HC supports a remote wakeup signal. This implementation does not support any such signal. The bit is hard-coded to `0.' InterruptRouting This bit is used for interrupt routing: 0: Interrupts routed to normal interrupt mechanism (INT). 1: Interrupts routed to SMI. HostControllerFunctionalState This field sets the Host Controller state. The Controller may force a state change from USB SUSPEND to USB RESUME after detecting resume signaling from a downstream port. States are: [9] RWC [8] INR [7:6] HCFS 00: USB RESET 01: USBRESUME 10: USBOPERATIONAL 11: USBSUSPEND [5] [4] BLE CLE BulkListEnable When set this bit enables processing of the Bulk list. Control Listenable When set this bit enables processing of the Control list. Isochronous Enable [3] ISE When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED. Periodic Listenable When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame. ControlBulkServiceRatio Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1 where N is the number of Control Endpoints (i.e. `00' = 1 Control Endpoint; `11' = 3 Control Endpoints) [2] PLE [1:0] CBR - 176 - W90P710 Host Controller Command Status Register REGISTER HcCommandStatus ADDRESS 0xFFF0_5008 R/W DESCRIPTION RESET VALUE R/W Host Controller Command Status Register 28 27 Reserved 19 11 Reserved 3 OCR DESCRIPTION 0x0000_0000 24 16 8 0 HCR 31 23 15 7 30 22 14 6 29 21 26 18 10 2 BLF 25 17 9 1 CLF 20 Reserved 13 12 5 Reserved 4 BITS [31:18] [17:16] [15:4] [3] Reserved SOC Reserved OCR Reserved ScheduleOverrunCount This field is increment every time the SchedulingOverrun bit in HcInterruptStatus is set. The count wraps from `11' to `00.' Reserved. Read/Write 0's OwnershipChangeRequest When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit is cleared by software. BulkListFilled Set to indicate there is an active ED on the Bulk List. The bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk List. ControlListFilled Set to indicate there is an active ED on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. HostControllerReset This bit is set to initiate the software reset. This bit is cleared by the Host Controller, upon completed of the reset operation. [2] BLF [1] CLF [0] HCR - 177 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Host Controller Interrupt Status Register All bits are set by hardware and cleared by software. REGISTER HcInterruptStatus ADDRESS 0xFFF0_500C R/W DESCRIPTION RESET VALUE R/W Host Controller Interrupt Status Register 28 27 26 25 17 9 1 WDH 0x0000_0000 24 16 8 0 SCO 31 Reserved 23 15 7 Reserved BITS 30 OCH 22 14 6 RHSC 29 21 13 5 FNO Reserved 20 19 18 Reserved 12 11 10 Reserved 4 3 2 URE RDT SOF DESCRIPTION [31] [30] [29:7] [6] Reserved OCH Reserved OwnershipChange This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. Reserved RootHubStatusChange RHSC This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed. FrameNumberOverflow Set when bit 15 of FrameNumber changes value. UnrecoverableError This event is not implemented and is hard-coded to `0.' ignored. ResumeDetected Writes are [5] FNO [4] URE [3] RDT Set when Host Controller detects resume signaling on a downstream port. StartOfFrame Set when the Frame Management block signals a `Start of Frame' event. [2] SOF - 178 - W90P710 Continued. BITS DESCRIPTION WritebackDoneHead [1] WDH Set after the Host HccaDoneHead. SchedulingOverrun [0] SCHO Set when the List Processor determines a Schedule Overrun has occurred. Controller has written HcDoneHead to Host Controller Interrupt Enable Register Writing a `1' to a bit in this register sets the corresponding bit, while writing a `0' leaves the bit unchanged. REGISTER HcInterruptEnable ADDRESS 0xFFF0_5010 R/W DESCRIPTION RESET VALUE R/W Host Controller Interrupt Enable Register 28 27 26 25 17 9 1 WDHE 0x0000_0000 24 16 8 0 SCHOE 31 MIE 23 15 7 Reserved BITS 30 OCE 22 14 6 RHCE 29 21 13 5 FNOE Reserved 20 19 18 Reserved 12 11 10 Reserved 4 3 2 UREE RDTE SOFE DESCRIPTION MasterInterruptEnable [31] MIE This bit is a global interrupt enable. A write of `1' allows interrupts to be enabled via the specific enable bits listed above. OwnershipChangeEnable [30] [29:7] [6] OCE Reserved RHSCE 0: Ignore 1: Enable interrupt generation due to Ownership Change. Reserved. Read/Write 0's RootHubStatusChangeEnable 0: Ignore 1: Enable interrupt generation due to Root Hub Status Change. - 179 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION FrameNumberOverflowEnable [5] FNOE 0: Ignore 1: Enable interrupt generation due to Frame Number Overflow. [4] UREE UnrecoverableErrorEnable This event is not implemented. All writes to this bit are ignored. ResumeDetectedEnable [3] RDTE 0: Ignore 1: Enable interrupt generation due to Resume Detected. StartOfFrameEnable [2] SOFE 0: Ignore 1: Enable interrupt generation due to Start of Frame. WritebackDoneHeadEnable [1] WDHE 0: Ignore 1: Enable interrupt generation due to Write-back Done Head. SchedulingOverrunEnable [0] SCHOE 0: Ignore 1: Enable interrupt generation due to Scheduling Overrun. Host Controller Interrupt Disable Register Writing a `1' to a bit in this register clears the corresponding bit, while writing a `0' to a bit leaves the bit unchanged. REGISTER HcInterruptEnable ADDRESS 0xFFF0_5014 R/W DESCRIPTION RESET VALUE R/W Host Controller Interrupt Disable Register 28 20 12 4 UREE 0x0000_0000 24 16 8 0 SCHOE 31 MIE 30 OCE 29 21 13 5 FNOE 27 Reserved 26 18 10 2 SOFE 25 17 9 1 WDHE 23 15 7 Reserved 22 14 6 RHSCE 19 Reserved 11 Reserved 3 RDTE - 180 - W90P710 BITS DESCRIPTION [31] MIE MasterInterruptEnable Global interrupt disable. A write of `1' disables all interrupts. OwnershipChangeEnable 0: Ignore 1: Disable interrupt generation due to Ownership Change. Reserved. Read/Write 0's RootHubStatusChangeEnable 0: Ignore 1: Disable interrupt generation due to Root Hub Status Change. FrameNumberOverflowEnable [30] [29:7] [6] OCE Reserved RHSCE [5] FNOE 0: Ignore 1: Disable interrupt generation due to Frame Number Overflow. UnrecoverableErrorEnable This event is not implemented. All writes to this bit will be ignored. ResumeDetectedEnable 0: Ignore 1: Disable interrupt generation due to Resume Detected. StartOfFrameEnable [4] UREE [3] RDTE [2] SOFE 0: Ignore 1: Disable interrupt generation due to Start of Frame. WritebackDoneHeadEnable [1] WDHE 0: Ignore 1: Disable interrupt generation due to Write-back Done Head. SchedulingOverrunEnable [0] SCHOE 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun. - 181 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Host Controller Communication Area Register REGISTER HcHCCA ADDRESS 0xFFF0_5018 R/W DESCRIPTION RESET VALUE R/W Host Controller Communication Area Register 0x0000_0000 28 HCCA 20 HCCA 12 HCCA 4 27 19 11 3 Reserved DESCRIPTION 31 23 15 7 30 22 14 6 29 21 13 5 26 18 10 2 25 17 9 1 24 16 8 0 BITS [31:8] [7:0] HCCA Reserved HCCA Pointer to HCCA base address. Reserved Host Controller Period Current ED Register REGISTER HcPeriodCurretED ADDRESS 0xFFF0_501C R/W DESCRIPTION RESET VALUE R/W Host Controller Period Current ED Register 0x0000_0000 28 PCED 31 23 15 7 30 22 14 6 PCED 29 21 13 5 27 19 PCED 26 18 10 2 25 17 9 1 24 16 8 0 20 12 PCED 11 3 4 BITS [31:4] [3:0] PCED Reserved DESCRIPTION PeriodCurrentED. Pointer to the current Periodic List ED. Reserved. Read/Write 0's - 182 - W90P710 Host Controller Control Head ED Register REGISTER HcControlHeadED ADDRESS 0xFFF0_5020 R/W DESCRIPTION RESET VALUE R/W Host Controller Control Head ED Register 28 CHED 0x0000_0000 24 16 8 0 31 23 15 7 30 22 14 6 CHED 29 21 13 5 27 19 CHED 26 18 10 2 Reserved 25 17 9 1 20 12 CHED 11 3 4 BITS [31:4] [3:0] CHED Reserved ControlHeadED DESCRIPTION Pointer to the Control List Head ED. Reserved Host Controller Control Current ED Register REGISTER HcControlCurrentED OFFSET ADDRESS 0xFFF0_5024 R/W DESCRIPTION RESET VALUE R/W Host Controller Control Current ED Register 0x0000_0000 28 CCED 31 23 15 7 30 22 14 6 CCED 29 21 13 5 27 19 CCED 26 18 10 2 Reserved 25 17 9 1 24 16 8 0 20 12 CCED 11 3 4 BITS [31:4] [3:0] CCED Reserved DESCRIPTION ControlCurrentED Pointer to the current Control List ED. Reserved. Read/Write 0's - 183 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Host Controller Bulk Head ED Register REGISTER HcBulkHEADED OFFSET ADDRESS 0xFFF0_5028 R/W DESCRIPTION RESET VALUE R/W Host Controller Bulk Head ED Register 28 BHED 0x0000_0000 24 16 8 0 31 23 15 7 30 22 14 6 BHED 29 21 13 5 27 19 BHED 26 18 10 2 Reserved 25 17 9 1 20 12 BHED 11 3 4 BITS [31:4] [3:0] BHED Reserved DESCRIPTION BulkHeadED. Pointer to the Bulk List Head ED. Reserved. Read/Write 0's Host Controller Bulk Current ED Register REGISTER HcBulkCurrentED OFFSET ADDRESS 0xFFF0_502C R/W DESCRIPTION RESET VALUE R/W Host Controller Bulk Current ED Register 28 BCED 0x0000_0000 24 16 8 0 31 23 15 7 30 22 14 6 BCED 29 21 13 5 27 19 BCED 26 18 10 2 Reserved 25 17 9 1 20 12 BCED 11 3 4 BITS [31:4] [3:0] BCED Reserved DESCRIPTION BulkCurrentED. Pointer to the current Bulk List ED. Reserved. Read/Write 0's - 184 - W90P710 Host Controller Done Head Register REGISTER HcDoneHead ADDRESS 0xFFF0_5030 R/W DESCRIPTION RESET VALUE R/W Host Controller Done Head Register 28 DOHD 0x0000_0000 25 17 9 1 24 16 8 0 31 23 15 7 30 22 14 6 DOHD 29 21 13 5 27 19 DOHD 26 18 10 2 Reserved 20 12 DOHD 11 3 4 BITS [31:4] [3:0] DOHD Reserved DESCRIPTION DoneHead. Pointer to the current Done List Head ED. Reserved. Read/Write 0's Host Controller Frame Interval Register REGISTER HcFmInterval ADDRESS 0xFFF0_5034 R/W DESCRIPTION RESET VALUE R/W Host Controller Frame Interval Register 0x0000_2ED F 24 16 8 0 31 FINTVT 30 22 14 Reserved 29 21 13 5 28 20 FSLDP 27 FSLDP 26 18 10 FINTV 25 17 9 1 23 15 7 19 11 3 FINTV 12 4 6 2 - 185 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS 31 FINTVT DESCRIPTION FrameIntervalToggle This bit is toggled by HCD when it loads a new value into Frame Interval. FSLargestDataPacket This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. Reserved. Read/Write 0's Frame Interval This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. [30:16] [15:14] [13:0] FSLDP Reserved FINTV Host Controller Frame Remaining Register REGISTER HcFmInterval ADDRESS 0xFFF0_5038 R/W DESCRIPTION RESET VALUE R Host Controller Frame Remaining Register 28 20 12 4 FRM 0x0000_0000 24 16 8 0 31 FRMT 30 22 14 Reserved 29 21 13 5 27 Reserved 26 18 10 FRM 25 17 9 1 23 15 7 19 Reserved 11 3 6 2 BITS [31] [30:14] FRMT Reserved FrameRemainingToggle DESCRIPTION Loaded with FrameIntervalToggle when Frame Remaining is loaded. Reserved. Read/Write 0's Frame Remaining When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. [13:0] FRM - 186 - W90P710 Host Controller Frame Number Register REGISTER HcFmNumber ADDRESS 0xFFF0_503C R/W DESCRIPTION RESET VALUE R Host Controller Frame Number Register 28 20 12 FRMN 0x0000_0000 24 16 8 0 31 23 15 7 30 22 14 6 29 21 13 5 27 Reserved 26 18 10 2 25 17 9 1 19 Reserved 11 3 FRMN 4 BITS [31:16] [15:0] Reserved FRMN FrameNumber DESCRIPTION Reserved. Read/Write 0's This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining. The count rolls over from `000Fh' to `0h.' Host Controller Periodic Start Register REGISTER HcPeriodicStart ADDRESS 0xFFF0_5040 R/W DESCRIPTION RESET VALUE R/W Host Controller Periodic Start Register 28 20 12 4 PERST 0x0000_0000 24 16 8 0 31 23 15 7 30 22 14 6 29 21 13 5 27 Reserved 26 18 10 PERST 25 17 9 1 19 Reserved 11 3 2 - 187 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS [31:14] [13:0] Reserved PERST Reserved. Read/Write 0's PeriodicStart DESCRIPTION This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. Host Controller Low Speed Threshold Register REGISTER HcLSThreshold ADDRESS 0xFFF0_5044 R/W DESCRIPTION RESET VALUE R/W Host Controller Register 28 20 27 Low Speed Threshold 0x0000_0628 31 23 15 7 30 22 14 29 21 26 18 25 17 24 16 8 0 13 Reserved 6 5 Reserved 19 Reserved 12 11 4 3 LsTreshold DESCRIPTION 10 9 LsThreshold 2 1 BITS [31:12] [11:0] Reserved LsTreshold Rsvd. Read/Write 0's LSThreshold This field contains a value used by the Frame Management block to determine whether or not a low speed transaction can be started in the current frame. Host Controller Root Hub Descriptor A Register This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. This bit should not be written during normal operation. REGISTER HcRhDescriptorA ADDRESS 0xFFF0_5048 R/W DESCRIPTION RESET VALUE R/W Host Controller Root Hub Descriptor A 0x0100.0002 Register - 188 - W90P710 31 23 15 7 30 22 14 Reserved 29 21 13 5 28 20 12 OCPM 27 POTPGT 26 18 10 DEVT 25 17 9 NPSW 24 16 8 PSWM 19 Reserved 11 OCPM 6 4 NDSP 3 2 1 0 BITS PowerOnToPowerGoodTime DESCRIPTION This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms. Only bits [25:24] is implemented as R/W. The remaining bits are read only as `0'. It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided. This field should be written to support system implementation. This field should always be written to a non-zero value. Reserved. Read/Write 0's NoOverCurrentProtection Global over-current reporting implemented in HYDRA-2. This bit should be written to support the external system port over-current implementation. 0 = Over-current status is reported 1 = Over-current status is not reported OverCurrentProtectionMode Global over-current reporting implemented in HYDRA-2. This bit should be written 0 and is only valid when NoOverCurrentProtection is cleared. 0 = Global Over-Current 1 = Individual Over-Current DeviceType HYDRA-4is not a compound device. NoPowerSwitching Global power switching implemented in HYDRA-2. This bit should be written to support the external system port power switching implementation. 0 = Ports are power switched. 1 = Ports are always powered on. PowerSwitchingMode Global power switching mode implemented in HYDRA-2. This bit is only valid when NoPowerSwitching is cleared. This bit should be written '0'. 0 = Global Switching 1 = Individual Switching NumberDownstreamPorts HYDRA-4 supports two downstream ports. [31:24] POTPGT [23:13] Reserved [12] NOCP [11] OCPM [10] DEVT [9] NPSW [8] PSWM [7:0] NDSP - 189 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Host Controller Root Hub Descriptor B Register This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE HcRhDescriptorB 0xFFF0_504C R/W Host Controller Root Hub Descriptor B Register 0x0000_0000 28 PPCM 31 23 15 7 30 22 14 6 29 21 13 5 27 19 PPCM 26 18 10 2 25 17 9 1 24 16 8 0 20 12 DEVRM 11 3 DEVRM 4 BITS DESCRIPTION PortPowerControlMask Global-power switching. This field is only valid if NoPowerSwitching is cleared and PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). 0 = Device not removable 1 = Global-power mask Port Bit relationship - Unimplemented ports are reserved, read/write '0'. 0 : Reserved 1 : Port 1 2 : Port 2 ... 15 : Port 15 DeviceRemoveable HYDRA-4 ports default to removable devices. 0 = Device not removable 1 = Device removable [31:16] PPCM [15:0] DEVRM Port Bit relationship 0 : Reserved 1 : Port 1 2 : Port 2 ... 15 : Port 15 Unimplemented ports are reserved, read/write '0'. - 190 - W90P710 Host Controller Root Hub Status Register This register is reset by the USBRESET state. REGISTER HcRhStstus OFFSET ADDRESS 0xFFF0_5050 R/W DESCRIPTION RESET VALUE R/W Host Controller Root Hub Status Register 28 20 Reserved 0x0000_0000 24 16 LPSC 31 23 15 DRWE 30 22 14 6 29 21 13 5 27 Reserved 26 18 10 2 25 17 OVIC 19 11 Reserved 12 4 Reserved 9 1 OVRCI 8 0 LOPS 7 3 BITS DESCRIPTION (Write) ClearRemoteWakeupEnable [31] [30:18] [17] CRWE Reserved OVIC Writing a '1' to this bit clears DeviceRemoteWakeupEnable. Writing a '1' has no effect. Reserved. Read/Write 0's OverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit. Writing a '0' has no effect. (Read) LocalPowerStatusChange Not supported. Always read '0'. [16] LPSC (Write) SetGlobalPower Write a '1' issues a SetGlobalPower command to the ports. Writing a '0' has no effect. (Read) DeviceRemoteWakeupEnable This bit enables ports' ConnectStatusChange as a remote wakeup event. 0 = disabled 1 = enabled (Write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoteWakeupEnable. Writing a '0' has no effect. [14:2] Reserved Reserved. Read/Write 0's [15] DRWE - 191 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION OverCurrentIndicator [1] OVRCI This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared. 0 = No over-current condition 1 = Over-current condition (Read) LocalPowerStatus Not Supported. Always read '0'. [0] LOPS (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect. Host Controller Root Hub Port Status [1][2] This register is reset by the USBRESET state. REGISTER HcRhPortStatus [1] HcRhPortStatus [2] ADDRESS 0xFFF0_5054 0xFFF0_5058 R/W DESCRIPTION RESET VALUE R/W Host Controller Root Hub Port Status [1] R/W Host Controller Root Hub Port Status [2] 28 20 PRSC 0x0000_0000 0x0000_0000 24 16 CSC 31 23 15 7 30 22 Reserved 14 6 Reserved 29 21 13 5 27 Reserved 19 POCIC 26 18 PSSC 25 17 PESC 12 Reserved 11 3 CPS 10 2 SPS 9 LSDA 4 SPR 1 SPE 8 PPS 0 DRM BITS [31:21] Reserved Reserved. Read/Write 0's PortResetStatusChange [20] PRSC DESCRIPTION This bit indicates that the port reset signal has completed. 0 = Port reset is not complete. 1 = Port reset is complete. - 192 - W90P710 Continued. BITS [19] POCIC DESCRIPTION PortOverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit. Writing a '0' has no effect. PortSuspendStatusChange This bit indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed. 1 = Port resume is complete. PortEnableStatusChange This bit indicates that the port has been disabled due to a hardware event (cleared PortEnableStatus). 0 = Port has not been disabled. 1 = PortEnableStatus has been cleared. ConnectStatusChange This bit indicates a connect or disconnect event has been detected. Writing a '1' clears this bit. Writing a '0' has no effect. 0 = No connect/disconnect event. 1 = Hardware detection of connect/disconnect event. Note: If DeviceRemoveable is set, this bit resets to '1'. Reserved. Read/Write 0's (Read) LowSpeedDeviceAttached This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device 1 = Low Speed device (Write) ClearPortPower Writing a '1' clears PortPowerStatus. Writing a '0' has no effect (Read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode. 0 = Port power is off. 1 = Port power is on. Note: If NoPowerSwitching is set, this bit is always read as '1'. (Write) SetPortPower Writing a '1' sets PortPowerStatus. Writing a '0' has no effect. [18] PSSC [17] PESC [16] CSC [15:10] Reserved [9] LSDA [8] PPS [7:5] Reserved Reserved. Read/Write 0's (Read) PortResetStatus 0 = Port reset signal is not active. 1 = Port reset signal is active. (Write) SetPortReset Writing a '1' sets PortResetStatus. Writing a '0' has no effect. [4] SPR - 193 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTION (Read) PortOverCurrentIndicator HYDRA-2 supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0 = No over-current condition 1 = Over-current condition (Write) ClearPortSuspend Writing a '1' initiates the selective resume sequence for the port. Writing a '0' has no effect. (Read) PortSuspendStatus 0 = Port is not suspended 1 = Port is selectively suspended (Write) SetPortSuspend Writing a '1' sets PortSuspendStatus. Writing a '0' has no effect. (Read) PortEnableStatus 0 = Port disabled. 1 = Port enabled. (Write) SetPortEnable Writing a '1' sets PortEnableStatus. Writing a '0' has no effect. (Read) CurrentConnectStatus 0 = No device connected. 1 = Device connected. [3] CPS [2] SPS [1] SPE [0] DRM NOTE: If DeviceRemoveable is set (not removable) this bit is always '1'. (Write) ClearPortEnable Writing '1' a clears PortEnableStatus. Writing a '0' has no effect. USB Operational Mode Enable Register This register selects which operational mode is enabled. Bits defined as write-only are read as 0's. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OperationalModeEnable 0xFFF0_5204 R/W USB Operational Mode Enable Register 0x0000_000 0 - 194 - W90P710 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 20 12 Reserved 27 Reserved 26 18 10 2 Reserved 25 17 9 1 24 16 8 SIEPD 0 DBREG 19 Reserved 11 3 OVRCUR 4 BITS BIT DESCRIPTION Reserved Reserved. Read/write 0 [31:9] [8] SIEPD SIE Pipeline Disable When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor. This is a failsafe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz. Reserved. Read/write 0 [7:4] Reserved OVRCURP (over current indicator polarity) [3] OVRCURP When the OVRCURP bit is clear, the OVRCUR non-inverted to input into USB host controller. In contrast, when the OVRCURP bit is set, the OVRCUR inverted to input into USB host controller. Reserved. Read/write 0 Data Buffer Region 16 When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes. [2:1] [0] Reserved DBREG 7.7.3 7.7.4 7.7.5 HCCA Endpoint Descriptor Transfer Descriptor 7.8 USB Device Controller The USB controller interfaces the AHB bus and the USB bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller through the AHB slave interface. For IN or OUT transfer, the USB controller needs to write data to memory or read data from memory through the AHB master interface. The USB controller also contains the USB transceiver to interface the USB. - 195 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.8.1 USB Endpoints It consists of four endpoints, designated EP0, EPA, EPB and EPC. Each is intended for a particular use as described below: EP0: the default endpoint uses control transfer (In/Out) to handle configuration and control functions required by the USB specification. Maximum packed size is 16 bytes. EPA: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint. EPB: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint. EPC: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint. 7.8.2 Standard device request The USB controller has built-in hard-wired state machine to automatically respond to USB standard device request. It also supports to detect the class and vendor requests. For Get Descriptor request and Class or Vendor command, the firmware will control these procedures. 7.8.3 USB Device Register Description USB Control Register (USB_CTL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_CTL 31 23 15 7 CCMD 0xFFF0_6000 30 22 14 6 VCMD 29 21 13 5 SIE_RCV R/W USB control register 28 Reserved 20 Reserved 12 Reserved 4 3 RWU_EN 2 SUSP 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 USB_EN SUS_TST USB_RST - 196 - W90P710 BITS DESCRIPTIONS [31:8] Reserved USB Class Command Decode Control Enable 0: Disable, the H/W circuit doesn't need to decode USB class command. It will return a stall status when it received a USB Class Command. 1: Enable, the H/W circuit decodes USB class command. It will assert an interrupt event when it received a USB Class Command. USB Vendor Command Decode Enable 0: Disable, the H/W circuit doesn't need to decode USB vendor command. It will return a stall status when it received a USB Vendor Command. 1: Enable, the H/W circuit decodes USB vendor command. It will assert an interrupt event when it received a USB Vendor Command. USB SIE Differential RCV Source 0: RCV generated by the SIE 1: RCV generated by the USB transceiver USB Suspend Accelerate Test 0: Normal Operation 1: USB Suspend Accelerate Test (Only for Test) USB Remote Wake-up Enable 0: Disable USB Remote Wake-Up Detect 1: Enable USB Remote Wake-Up Detect USB Suspend Detect Enable 0: Disable USB Suspend Detect 1: Enable USB Suspend Detect USB Engine Reset 0: Normal operation 1: Reset USB Engine USB Engine Enable 0: disable USB Engine 1: enable USB Engine Note: set this bit to "0", the device is absent from host. After set this bit to "1", the host will detect a device attached. [7] CCMD [6] VCMD [5] SIE_RCV [4] SUS_TST [3] RWU_EN [2] SUSP [1] USB_RST [0] USB_EN - 197 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Class or Vendor command Register (USB_CVCMD) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_CVCMD 0xFFF0_6004 R/W USB class or vendor command register 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 CVI_LG 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:5] [4:0] CVI_LG Reserved Byte Length for Class and Vendor Command and Get Descriptor Return Data Packet USB Interrupt Enable Register (USB_IE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IE 31 23 15 RUM_CLKI 7 CLAI 0xFFF0_6008 30 22 14 RST_ENDI 6 GSTRI R/W 29 21 13 USB interrupt enable register 28 Reserved 20 Reserved 12 USB_BTI 4 GDEVI 11 CVSI 3 ERRI 10 CDII 2 RUMI 27 19 26 18 0x0000_0000 25 17 9 CDOI 1 SUSI 24 16 8 VENI 0 RSTI USB_CGI 5 GCFGI - 198 - W90P710 BITS DESCRIPTIONS [31:16] [15] RUM_CLKI Reserved Interrupt enable for RESUME (for clock is stopped) 0: Disable 1: Enable Interrupt enable for USB reset end 0: Disable 1: Enable Interrupt Enable for Device Configured 0: Disable 1: Enable Note: the interrupt occurs when device configured or dis-configured. Interrupt Enable for USB Bus Transition 0: Disable 1: Enable Interrupt Enable Control for Status Phase of Class or Vendor Command 0: Disable 1: Enable Interrupt Enable Control for Data-In of Class or Vendor Command 0: Disable 1: Enable Interrupt Enable Control for Data-Out of Class or Vendor Command 0: Disable 1: Enable Interrupt Enable Control for USB Vendor Command 0: Disable 1: Enable Interrupt Enable Control for USB Class Command 0: Disable 1: Enable Interrupt Enable Control for USB Get_String_Descriptor Command 0: Disable 1: Enable Interrupt Enable Control for USB Get_Configuration_Descriptor Command 0: Disable 1: Enable [14] RST_ENDI [13] USB_CGI [12] USB_BTI [11] CVSI [10] CDII [9] CDOI [8] VENI [7] CLAI [6] GSTRI [5] GCFGI - 199 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [4] GDEVI Interrupt Enable Control for USB Get_Device_Descriptor Command 0: Disable 1: Enable Interrupt Enable Control for USB Error Detect 0: Disable 1: Enable Interrupt Enable Control for USB Resume Detect 0: Disable 1: Enable Interrupt Enable Control for USB Suspend Detect 0: Disable 1: Enable Interrupt Enable Control for USB Reset Command Detect 0: Disable 1: Enable [3] ERRI [2] RUMI [1] SUSI [0] RSTI USB Interrupt status Register (USB_IS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IS 0xFFF6_000C R USB interrupt status register 0x0000_0000 31 23 15 RUM_CLK S 7 CLAS 30 22 14 RSTENDS 6 GSTRS 29 21 13 USB_CGS 5 GCFGS 20 28 Reserved 19 Reserved 12 USB_BTS 4 GDEVS 27 18 11 CVSS 3 ERRS 26 25 17 24 16 8 VENS 0 RSTS 10 CDIS 2 RUMS 9 CDOS 1 SUSS - 200 - W90P710 BITS DESCRIPTIONS [31:16] Reserved Interrupt status for RESUME (for clock is stopped) [15] RUM_CLKS 0: No Interrupt Generated 1: Interrupt Generated Interrupt status for USB reset end [14] RSTENDS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Device Configured [13] USB_CGS 0: No Interrupt Generated 1: Interrupt Generated(configured and dis-configured) Interrupt Status for USB Bus Transition [12] USB_BTS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for Status Phase of Class or Vendor Command [11] CVSS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for Data-In of Class or Vendor Command [10] CDIS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for Data-Out of Class or Vendor Command [9] CDOS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Vendor Command [8] VENS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Class Command [7] CLAS 0: No Interrupt Generated 1: Interrupt Generated - 201 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS Interrupt Status for USB Get_String_Descriptor Command [6] GSTRS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Get_Configuration_Descriptor Command [5] GCFGS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Get_Device_Descriptor Command [4] GDEVS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Error Detect [3] ERRS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Resume Detect [2] RUMS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Suspend Detect [1] SUSS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Reset Command Detect [0] RSTS 0: No Interrupt Generated 1: Interrupt Generated USB Interrupt Status Clear (USB_IC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IC 0xFFF6_0010 R/W USB interrupt status clear register 0x0000_0000 - 202 - W90P710 31 23 15 RUM_CLK C 7 CLAC 30 22 14 RSTENDC 6 GSTRC 29 21 13 USB_CGC 5 GCFGC 28 Reserved 20 Reserved 12 USB_BTC 4 GDEVC 27 19 11 CVSC 3 ERRC 26 18 10 CDIC 2 RUMC 25 17 9 CDOC 1 SUSC 24 16 8 VENC 0 RSTC BITS DESCRIPTIONS [31:16] [15] RUM_CLKC Reserved Interrupt status clear for RESUME (for clock is stopped) 0: NO Operation 1: Clear Interrupt Status Interrupt status clear for USB reset end 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Device Configured 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Bus Transition 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for Status Phase of Class or Vendor Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for Data-In of Class or Vendor Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for Data-Out of Class or Vendor Command 0: NO Operation 1: Clear Interrupt Status [14] RSTENDC [13] USB_CGC [12] USB_BTC [11] CVSC [10] CDIC [9] CDOC - 203 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [8] VENC Interrupt Status Clear for USB Vendor Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Class Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Get_String_Descriptor Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Get_Configuration_Descriptor Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Get_Device_Descriptor Command 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Error Detect 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Resume Detect 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Suspend Detect 0: NO Operation 1: Clear Interrupt Status Interrupt Status Clear for USB Reset Command Detect 0: NO Operation 1: Clear Interrupt Status [7] CLAC [6] GSTRC [5] GCFGC [4] GDEVC [3] ERRC [2] RUMC [1] SUSC [0] RSTC USB Interface and String Register (USB_IFSTR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IFSTR 0xFFF06014 R/W USB interface and string register 0x0000_0000 - 204 - W90P710 31 23 15 7 STR4_EN 30 22 14 6 STR3_EN 29 21 13 Reserved 5 STR2_EN 4 STR1_EN 3 INF4_EN 2 INF3_EN 28 27 26 18 10 25 17 9 STR6_EN 1 INF2_EN 24 16 8 STR5_EN 0 INF1_EN Reserved 20 19 Reserved 12 11 BITS DESCRIPTIONS [31:10] Reserved USB String Descriptor-6 Control [9] STR6_EN 0: Disable 1: Enable USB String Descriptor-5 Control [8] STR5_EN 0: Disable 1: Enable USB String Descriptor-4 Control [7] STR4_EN 0: Disable 1: Enable USB String Descriptor-3 Control [6] STR3_EN 0: Disable 1: Enable USB String Descriptor-2 Control [5] STR2_EN 0: Disable 1: Enable USB String Descriptor-1 Control [4] STR1_EN 0: Disable 1: Enable - 205 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS USB Interface-4 Control [3] INF4_EN 0: Disable 1: Enable USB Interface-3 Control [2] INF3_EN 0: Disable 1: Enable USB Interface-2 Control [1] INF2_EN 0: Disable 1: Enable USB Interface-1 Control [0] INF1_EN 0: Disable 1: Enable USB Control transfer-out port 0 (USB_ODATA0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_ODATA0 0xFFF06018 R USB control register transfer-out port 0 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 ODATA0 20 ODATA0 12 ODATA0 4 ODATA0 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] ODATA0 Control Transfer-out data 0 - 206 - W90P710 USB Control transfer-out port 1 (USB_ODATA1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_ODATA1 0xFFF0601C R USB control transfer-out port 1 register 28 ODATA1 20 ODATA1 12 ODATA1 4 ODATA1 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 24 16 8 0 BITS DESCRIPTIONS [31:0] ODATA1 Control Transfer-out data 1 USB Control transfer-out port 2 (USB_ODATA2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_ODATA2 0xFFF06020 R USB control transfer-out port 2 register 28 ODATA2 20 ODATA2 12 ODATA2 4 ODATA2 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 24 16 8 0 BITS DESCRIPTIONS [31:0] ODATA2 Control Transfer-out data 2 - 207 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Control transfer-out port 3 (USB_ODATA3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_ODATA3 31 23 15 7 0xFFF06024 30 22 14 6 29 21 13 5 R USB control register 28 ODATA3 20 ODATA3 12 ODATA3 4 ODATA3 3 11 19 27 transfer-out port 3 0x0000_0000 24 16 8 0 26 18 10 2 25 17 9 1 BITS DESCRIPTIONS [31:0] ODATA3 Control Transfer-out data 3 USB Control transfer-in data port0 Register (USB_IDATA0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IDATA0 31 23 15 7 0xFFF06028 30 22 14 6 29 21 13 5 R/W USB transfer-in data port0 register 28 IDATA0 20 IDATA0 12 IDATA0 4 IDATA0 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 BITS DESCRIPTIONS [31:6] IDATA0 Control transfer-in data0 - 208 - W90P710 USB Control transfer-in data port 1 Register (USB_IDATA1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IDATA1 31 23 15 7 0xFFF0602C 30 22 14 6 29 21 13 5 R/W USB control transfer-in data port 1 28 IDATA1 20 IDATA1 12 IDATA1 4 IDATA1 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 BITS DESCRIPTIONS [31:6] IDATA1 Control transfer-in data1 USB Control transfer-in data port 2 Register (USB_IDATA2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IDATA2 31 23 15 7 0xFFF06030 30 22 14 6 29 21 13 5 R/W USB control transfer-in data port 2 28 IDATA2 20 IDATA2 12 IDATA2 4 IDATA2 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 BITS DESCRIPTIONS [31:6] IDATA2 Control transfer-in data2 - 209 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Control transfer-in data port 3 Register (USB_IDATA3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_IDATA3 31 23 15 7 0xFFF06034 30 22 14 6 29 21 13 5 R/W USB control transfer-in data port 3 28 IDATA3 20 IDATA3 12 IDATA3 4 IDATA3 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 BITS DESCRIPTIONS [31:6] IDATA3 Control transfer-in data3 USB SIE Status Register (USB_SIE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_SIE 31 23 15 7 0xFFF06038 30 22 14 6 29 21 13 5 R USB SIE status Register 28 20 12 4 27 Reserved 19 Reserved 11 Reserved 3 2 1 10 9 18 17 26 25 0x0000_0000 24 16 8 0 USB_DMS Reserved USB_DPS - 210 - W90P710 BITS DESCRIPTIONS [31:2] [1] USB_DPS Reserved USB Bus D+ Signal Status 0: USB Bus D+ Signal is low 1: USB Bus D+ Signal is high USB Bus D- Signal Status 0: USB Bus D- Signal is low 1: USB Bus D- Signal is high [0] USB_DMS USB Engine Register (USB_ENG) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_ENG 31 23 15 7 0xFFF0603C 30 22 14 6 Reserved 29 21 13 5 R/W 28 20 12 4 USB Engine Register 27 Reserved 19 Reserved 11 Reserved 3 SDO_RD 2 CV_LDA 1 10 9 26 18 25 17 0x0000_0000 24 16 8 0 CV_DAT CV_STL BITS DESCRIPTIONS [31:4] Reserved Setup or Bulk-Out Data Read Control 0: NO Operation 1: Read Setup or Bulk-Out Data from USB Host NOTE: this bit will auto clear after 32 HCLK USB Class and Vendor Command Last Data Packet Control 0: NO Operation 1: Last Data Packet for Data Input of Class and Vendor Command NOTE: this bit will auto clear after 32 HCLK [3] SDO_RD [2] CV_LDA - 211 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [1] CV_STL USB Class and Vendor Command Stall Control 0: NO Operation 1: Return Stall for Class and Vendor Command NOTE: this bit will auto clear after 32 HCLK USB Class and Vendor Command return data control 0: NO Operation 1: The Data Packet for Data Input of Class and Vendor Command or Get Descriptor command is ready. NOTE: this bit will auto clear after 32 HCLK [0] CV_DAT USB Control Register (USB_CTLS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_CTLS 0xFFF06040 R USB control transfer status register 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 CONF 4 27 19 11 3 26 18 10 2 CTLRPS 25 17 9 1 24 16 8 0 ITS DESCRIPTIONS [31:16] [15:8] [7:5] [4:0] CTLRPS CONF Reserved USB configured value Reserved Control transfer received packet size - 212 - W90P710 USB Configured Value Register (USB_CONFD) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_CONFD 0xFFF06044 R/W USB Configured Value register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 CONFD 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:8] [7:0] CONFD Reserved Software configured value USB Endpoint A Information Register (EPA_INFO) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_INFO 31 Reserved 23 15 7 0xFFF06048 30 22 14 EPA_ALT 6 EPA_CFG 5 29 21 13 R/W USB endpoint A information register 28 EPA_DIR 20 EPA_MPS 12 4 11 3 10 EPA_INF 2 1 EPA_NUM 9 19 27 Reserved 18 26 0x0000_0000 25 17 24 16 8 0 EPA_TYPE EPA_MPS - 213 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31] Reserved Endpoint A type 00: reserved 01: bulk 10: interrupt 11: isochronous Endpoint A direction 0: OUT 1: IN Reserved EPA_MPS EPA_ALT EPA_INF EPA_CFG EPA_NUM Endpoint A max. packet size Endpoint A alternative setting (READ ONLY) Endpoint A interface Endpoint A configuration Endpoint A number [30:29] EPA_TYPE [28] [27:26] [25:16] [15:12] [11:8] [7:4] [3:0] EPA_DIR USB Endpoint A Control Register (EPA_CTL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_CTL 31 23 15 7 Reserved 0xFFF0604C 30 22 14 6 EPA_ZERO 29 21 13 5 R/W USB endpoint A control register 28 Reserved 20 Reserved 12 Reserved 4 3 2 EPA_RDY 11 10 19 18 27 26 0x0000_0000 25 17 9 1 EPA_RST 24 16 8 0 EPA_EN EPA_STL_CLR EPA_THRE EPA_STL - 214 - W90P710 BITS DESCRIPTIONS [31:6] [6] [5] EPA_ZERO EPA_STL_CLR Reserved Send zero length packet to HOST CLEAR the Endpoint A stall(WRITE ONLY) Endpoint A threshold (only for ISO) [4] EPA_THRE 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] [2] [1] [0] EPA_STL EPA_RDY EPA_RST EPA_EN Set the Endpoint A stall The memory is ready for Endpoint A to access Endpoint A reset Endpoint A enable USB Endpoint A interrupt enable Register (EPA_IE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_IE 0xFFF06050 R/W USB endpoint register A Interrupt Enable 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 EPA_CF_IE 28 20 12 4 EPA_BUS_ERR_I E 27 Reserved 19 Reserved 11 Reserved 3 EPA_DMA_IE 26 18 10 2 EPA_ALT_IE 25 17 9 1 EPA_TK_IE 24 16 8 0 EPA_STL_IE Reserved - 215 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPA_CF_IE EPA_BUS_ERR_IE EPA_DMA_IE EPA_ALT_IE EPA_TK_IE EPA_STL_IE Reserved Endpoint A clear feature interrupt enable Endpoint A system bus error interrupt enable Endpoint A DMA transfer complete interrupt enable Endpoint A alternate setting interrupt enable Endpoint A token input interrupt enable Endpoint A stall interrupt enable USB Endpoint A Interrupt Clear Register (EPA_IC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_IC 0xFFF06054 W USB endpoint register 28 Reserved 20 Reserved 12 Reserved 4 EPA_BUS_ERR_I C A interrupt clear 0x0000_0000 31 23 15 7 Reserved 30 22 14 6 29 21 13 5 EPA_CF_IC 27 19 11 3 EPA_DMA_IC 26 18 10 2 EPA_ALT_IC 25 17 9 1 EPA_TK_IC 24 16 8 0 EPA_STL_IC BITS DESCRIPTIONS [31:6] [5] [4] [3] EPA_CF_INT_IC EPA_BUS_ERR_IC EPA_DMA_IC Reserved Endpoint A clear feature interrupt clear Endpoint A system bus error interrupt clear Endpoint A DMA transfer complete interrupt clear - 216 - W90P710 Continued. BITS DESCRIPTIONS [2] [1] [0] EPA_ALT_IC EPA_TK_IC EPA_STL_IC Endpoint A alternate setting interrupt clear Endpoint A token input interrupt clear Endpoint A stall interrupt clear USB Endpoint A Interrupt Status Register (EPA_IS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_IS 0xFFF06058 R USB endpoint A interrupt status register 0x0000_0000 31 23 15 7 Reserved 30 22 14 6 29 21 13 5 EPA_CF_IS 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 EPA_ALT_IS 25 17 9 1 EPA_TK_IS 24 16 8 0 EPA_STL_IS EPA_BUS_ERR_IS EPA_DMA_IS BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPA_CF_IS EPA_BUS_ERR_IS EPA_DMA_IS EPA_ALT_IS EPA_TK_IS EPA_STL_IS Reserved Endpoint A clear feature interrupt status Endpoint A system bus error interrupt status Endpoint A DMA transfer complete interrupt status Endpoint A alternative setting interrupt status Endpoint A token interrupt status Endpoint A stall interrupt status - 217 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Endpoint A Address Register (EPA_ADDR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_ADDR 0xFFF0605C R/W USB endpoint A address register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 27 26 18 10 2 25 17 9 1 24 16 8 0 EPA_ADDR 20 19 EPA_ADDR 12 4 11 3 EPA_ADDR EPA_ADDR BITS DESCRIPTIONS [31:0] EPA_ADDR Endpoint A transfer address USB Endpoint A transfer length Register (EPA_LENTH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_LENTH 0xFFF06060 R/W USB endpoint register A transfer length 0x0000_0000 31 23 15 7 30 22 Reserved 14 6 29 21 13 5 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 EPA_LENTH EPA_LENTH EPA_LENTH - 218 - W90P710 BITS DESCRIPTIONS [31:20] [19:0] EPA_LENTH Reserved Endpoint A transfer length USB Endpoint B Information Register (EPB_INFO) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_INFO 31 Reserved 23 15 7 0xFFF06064 30 22 14 EPB_ALT 6 EPB_CFG 5 29 21 13 R/W USB endpoint B information register 28 EPB_DIR 20 EPB_MPS 12 4 11 3 10 EPB_INF 2 1 EPB_NUM DESCRIPTIONS 0x0000_0000 25 17 9 24 16 8 0 27 Reserved 19 26 18 EPB_TYPE EPB_MPS BITS [31] Reserved Endpoint B type 00: reserved [30:29] EPB_TYPE 01: bulk 10: interrupt 11: isochronous Endpoint B direction [28] EPB_DIR 0: OUT 1: IN [27:26] [25:16] EPB_MPS Reserved Endpoint B max. packet size - 219 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [15:12] [11:8] [7:4] [3:0] EPB_ALT EPB_INF EPB_CFG EPB_NUM Endpoint B alternative setting (READ ONLY) Endpoint B interface Endpoint B configuration Endpoint B number USB Endpoint B Control Register (EPB_CTL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_CTL 0xFFF06068 R/W USB endpoint B control register 0x0000_0000 31 23 15 7 Reserved 30 22 14 6 EPB_ZERO 29 21 13 5 EPB_STL_CLR 28 Reserved 20 Reserved 12 Reserved 4 EPB_THRE 27 19 11 3 EPB_STL 26 18 10 2 EPB_RDY 25 17 9 1 EPB_RST 24 16 8 0 EPB_EN BITS DESCRIPTIONS [31:7] [6] [5] EPB_ZERO EPB_STL_CLR Reserved Send zero length packet back to HOST Clear the Endpoint B stall(WRITE ONLY) Endpoint B threshold (only for ISO) [4] EPB_THRE 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] EPB_STL Set the Endpoint B stall - 220 - W90P710 Continued. BITS DESCRIPTIONS [2] [1] [0] EPB_RDY EPB_RST EPB_EN The memory is ready for Endpoint B to access Endpoint B reset Endpoint B enable USB Endpoint B interrupt enable Register (EPB_IE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_IE 0xFFF0606C R/W USB endpoint register B Interrupt Enable 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 EPB_CF_IE 28 20 12 4 EPB_BUS_ERR_IE 27 Reserved 19 Reserved 11 Reserved 3 EPB_DMA_IE 26 18 10 2 EPB_ALT_IE 25 17 9 1 EPB_TK_IE 24 16 8 0 EPB_STL_I E Reserved BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPB_CF_IE EPB_BUS_ERR_IE EPB_DMA_IE EPB_ALT_IE EPB_TK_IE EPB_STL_IE Reserved Endpoint B clear feature interrupt enable Endpoint B system bus error interrupt enable Endpoint B DMA transfer complete interrupt enable Endpoint B alternate setting interrupt enable Endpoint B token input interrupt enable Endpoint B stall interrupt enable - 221 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Endpoint B Interrupt Clear Register (EPB_IC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_IC 0xFFF06070 W USB endpoint register B interrupt clear 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 EPB_CF_IC 28 20 12 4 EPB_BUS_ERR_IC 27 Reserved 19 Reserved 11 Reserved 3 EPB_DMA_IC 26 18 10 2 EPB_ALT_IC 25 17 9 1 EPB_TK_IC 24 16 8 0 EPB_STL_IC Reserved BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPB_CF_IC EPB_BUS_ERR_IC EPB_DMA_IC EPB_ALT_IC EPB_TK_IC EPB_STL_IC Reserved Endpoint B clear feature interrupt clear Endpoint B system bus error interrupt clear Endpoint B DMA transfer complete interrupt clear Endpoint B alternate setting interrupt clear Endpoint B token input interrupt clear Endpoint B stall interrupt clear USB Endpoint B Interrupt Status Register (EPB_IS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_IS 0xFFF06074 R USB endpoint register B interrupt status 0x0000_0000 - 222 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 EPB_CF_IS 28 20 12 4 EPB_BUS_ERR_IS 27 Reserved 19 Reserved 11 Reserved 3 EPB_DMA_IS 26 18 10 2 EPB_ALT_IS 25 17 9 1 EPB_TK_IS 24 16 8 0 EPB_STL_IS Reserved BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPB_CF_IS EPB_DMA_IS EPB_DMA_IS EPB_ALT_IS EPB_TK_IS EPB_STL_IS Reserved Endpoint B clear feature interrupt status Endpoint B system bus error interrupt status Endpoint B DMA transfer complete interrupt status Endpoint B alternative setting interrupt status Endpoint B token interrupt status Endpoint B stall interrupt status USB Endpoint B Address Register (EPB_ADDR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_ADDR 31 23 15 7 0xFFF06078 30 22 14 6 29 21 13 5 R/W USB endpoint B address register 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 EPB_ADDR EPB_ADDR EPB_ADDR EPB_ADDR Publication Release Date: January 17, 2005 Revision A.2 - 223 - W90P710 BITS DESCRIPTIONS [31:0] EPB_ADDR Endpoint B transfer address USB Endpoint B transfer length Register (EPB_LENTH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_LENTH 0xFFF0607C R/W USB endpoint register B transfer length 0x0000_0000 31 23 15 7 30 22 Reserved 14 6 29 21 13 5 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 EPB_LENTH EPB_LENTH EPB_LENTH BITS DESCRIPTIONS [31:20] [19:0] EPB_LENTH Reserved Endpoint B transfer length USB Endpoint C Information Register (EPC_INFO) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_INFO 0xFFF06080 R/W USB endpoint register C information 0x0000_0000 - 224 - W90P710 31 Reserved 23 15 7 30 22 14 6 29 21 13 5 28 EPC_DIR 20 EPC_MPS 12 4 27 Reserved 19 11 3 26 18 10 25 17 9 EPC_INF 1 24 16 8 0 EPC_TYPE EPC_MPS EPC_ALT 2 EPC_CFG EPC_NUM BITS DESCRIPTIONS [31] Reserved Endpoint C type 00: reserved [30:29] EPC_TYPE 01: bulk 10: interrupt 11: isochronous Endpoint C direction [28] EPC_DIR 0: OUT 1: IN [27:26] [25:16] [15:12] [11:8] [7:4] [3:0] EPC_MPS EPC_ALT EPC_INF EPC_CFG EPC_NUM Reserved Endpoint C max. packet size Endpoint C alternative setting (READ ONLY) Endpoint C interface Endpoint C configuration Endpoint C number - 225 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Endpoint C Control Register (EPC_CTL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_CTL 0xFFF06084 R/W USB endpoint C control register 0x0000_0000 31 23 15 7 Reserved 30 22 14 6 EPC_ZERO 29 21 13 5 EPC_STL_CLR 28 Reserved 20 Reserved 12 Reserved 4 EPC_THRE 27 19 11 3 EPC_STL 26 18 10 2 EPC_RDY 25 17 9 1 EPC_RST 24 16 8 0 EPC_EN BITS DESCRIPTIONS [31:7] [6] [5] EPC_ZERO EPC_STL_CLR Reserved Send zero length packet back to HOST Clear the Endpoint C stall(WRITE ONLY) Endpoint C threshold (only for ISO) [4] EPC_THRE 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] [2] [1] [0] EPC_STL EPC_RDY EPC_RST EPC_EN Set the Endpoint C stall The memory is ready for Endpoint C to access Endpoint C reset Endpoint C enable - 226 - W90P710 USB Endpoint C interrupt enable Register (EPC_IE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_IE 0xFFF06088 R/ W USB endpoint register C Interrupt Enable 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 EPC_CF_IE 28 20 12 4 EPC_BUS_ERR_IE 27 Reserved 19 Reserved 11 Reserved 3 EPC_DMA_IE 26 18 10 2 EPC_ALT_IE 25 17 9 1 EPC_TK_IE 24 16 8 0 EPC_STL_IE Reserved BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPC_CF_IE EPC_DMA_IE EPC_DMA_IE EPC_ALT_IE EPC_TK_IE EPC_STL_IE Reserved Endpoint C clear feature interrupt enable Endpoint C system bus error interrupt enable Endpoint C DMA transfer complete interrupt enable Endpoint C alternate setting interrupt enable Endpoint C token input interrupt enable Endpoint C stall interrupt enable USB Endpoint C Interrupt Clear Register (EPC_IC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_IC 0xFFF0608C W USB endpoint register C interrupt clear 0x0000_0000 - 227 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 Reserved 30 22 14 6 29 21 13 5 EPC_CF_IC 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 EPC_ALT_IC 25 17 9 1 EPC_TK_IC 24 16 8 0 EPC_STL_IC EPC_BUS_ERR EPC_DMA_IC _IC BITS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPC_CF_IC EPC_DMA_IC EPC_DMA_IC EPC_ALT_IC EPC_TK_IC EPC_STL_IC Reserved Endpoint C clear feature interrupt clear Endpoint C system bus error interrupt clear Endpoint C DMA transfer complete interrupt clear Endpoint C alternate setting interrupt clear Endpoint C token input interrupt clear Endpoint C stall interrupt clear USB Endpoint C Interrupt Status Register (EPC_IS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_IS 0xFFF06090 R USB endpoint register C interrupt status 0x0000_0000 - 228 - W90P710 31 23 15 7 Reserved BITS 30 22 14 6 29 21 13 5 EPC_CF_IS 28 20 12 4 27 Reserved 19 Reserved 11 Reserved 3 26 18 10 2 EPC_ALT_IS 25 17 9 1 EPC_TK_IS 24 16 8 0 EPC_STL_IS EPC_BUS_ERR_IS EPC_DMA_IS DESCRIPTIONS [31:6] [5] [4] [3] [2] [1] [0] EPC_CF_IS EPC_BUS_ERR_IS EPC_DMA_IS EPC_ALT_IS EPC_TK_IS EPC_STL_IS Reserved Endpoint C clear feature interrupt status Endpoint A system bus error interrupt status Endpoint A DMA transfer complete interrupt status Endpoint A alternative setting interrupt status Endpoint A token interrupt status Endpoint A stall status USB Endpoint C Address Register (EPC_ADDR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_ADDR 31 23 15 7 0xFFF0_6094 30 22 14 6 29 21 13 5 R/W USB endpoint C address register 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 EPC_ADDR EPC_ADDR EPC_ADDR EPC_ADDR - 229 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:0] EPC_ADDR Endpoint C transfer address USB Endpoint C transfer length Register (EPC_LENTH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_LENTH 0xFFF0_6098 R/W USB endpoint C transfer length register 0x0000_0000 31 23 15 7 30 22 Reserved 14 6 29 21 13 5 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 EPC_LENTH EPC_LENTH EPC_LENTH BITS DESCRIPTIONS [31:20] [19:0] EPC_LENTH Reserved Endpoint C transfer length USB Endpoint A Remain transfer length Register (EPA_XFER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_XFER 0xFFF0_609C R/W USB endpoint A remain transfer length register 0x0000_0000 - 230 - W90P710 31 23 15 7 30 22 Reserved 14 6 29 21 13 5 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 EPA_XFER EPA_XFER EPA_XFER BITS DESCRIPTIONS [31:20] [19:0] EPA_XFER Reserved Endpoint A remain transfer length USB Endpoint A Remain packet length Register (EPA_PKT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPA_PKT 0xFFF0_60A0 R/W USB endpoint A remain packet length register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 Reserved 5 28 Reserved 20 Reserved 12 4 27 19 11 3 EPA_PKT 26 18 10 2 25 17 9 EPA_PKT 1 24 16 8 0 BITS Descriptions Reserved EPA_PKT Endpoint A remain packet length [31:10] [9:0] - 231 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Endpoint B Remain transfer length Register (EPB_XFER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_XFER 0xFFF0_60A4 R/W USB endpoint B remain transfer length register 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 Reserved 14 6 29 21 13 5 24 16 8 0 EPB_XFER EPB_XFER EPB_XFER BITS DESCRIPTIONS [31:20] [19:0] EPB_XFER Reserved Endpoint B remain transfer length USB Endpoint B Remain packet length Register (EPB_PKT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPB_PKT 0xFFF0_60A8 R/W USB endpoint B remain packet length register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 Reserved 5 28 Reserved 20 Reserved 12 4 27 19 11 3 EPB_PKT 26 18 10 2 25 17 9 EPB_PKT 1 24 16 8 0 - 232 - W90P710 BITS DESCRIPTIONS [31:10] [9:0] EPB_PKT Reserved Endpoint B remain packet length USB Endpoint C Remain transfer length Register (EPC_XFER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_XFER 0xFFF0_60AC R/W USB endpoint C remain transfer length register 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 Reserved 14 6 29 21 13 5 24 16 8 0 EPC_XFER EPC_XFER EPC_XFER BITS DESCRIPTIONS [31:20] [19:0] EPC_XFER Reserved Endpoint C remain transfer length USB Endpoint C Remain packet length Register (EPC_PKT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_PKT 0xFFF0_60B0 R/W USB endpoint length register C remain packet 0x0000_0000 - 233 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 Reserved 5 28 20 12 4 27 Reserved 19 Reserved 11 3 EPC_PKT 26 18 10 2 25 17 9 EPC_PKT 1 24 16 8 0 BITS DESCRIPTIONS [31:10] [9:0] EPC_PKT Reserved Endpoint C remain packet length - 234 - W90P710 7.9 SDIO Host Controller The SDIO host controller of W90P710 supports Secure Digital card devices (SD, SDIO & MMC). The SDIO controller also supports DMA function to reduce the intervention of CPU for data transfer between flash memory card and system memory. There are two 512B internal buffers embedded in the SDIO host controller to buffer the data temporally for DMA transfer between flash memory card and system memory. The SDIO host controller features are shown as below: Directly connect to Secure Digital (SD, MMC or SDIO) flash memory card. Supports DMA function to accelerate the data transfer between the internal buffer, external SDRAM, and flash memory card. Two 512 bytes internal buffers are embedded inside of the SDIO host controller. No SPI mode. 7.9.1 Functional Description SDIO controller provides three signals, CLK, CMD and DAT[3:0], to all SD cards. CLK is a clock output signal. CM and DAT[3:0] are bi-direction command and data signals, respectively. The frequency of CLK is equal to (engine clock frequency)/(SD_CLK+1), where SD_CLK is the value of the SD clock control register. To save power, CLK is active only when there are activities between SDIO host controller and SD cards. Otherwise, CLK keeps inactive state (LOW). According to the SD specification, SDIO host controller provides several operations to communicate with SD Cards efficiently. The CPU writes to the SD access control register to setup the operations. When the command output enable bit of SD access control register is set, SDIO host controller transfers a 48-bit command to one or more SD cards. When the transfer is done, this bit is reset to 0 automatically. For a 48-bits command, the 6-bits command number is coming from SD CMD code register and the 32-bits command argument is coming from SD command argument 1-4 registers. All other bits (including start bit, end bit and the CRC-7bits) are generated by SDIO host controller H/W circuit. When the response input enable bit of SD access control register is set, SDIO host controller waits for a 48-bit response form one or more SD cards. When a 48-bit response is received, this bit is reset to 0 automatically. The first 40 bits of the received response are stored into SD received response token1 - 5 registers. The last 8 bits are CRC-7 bits and end bit. SDIO host controller H/W circuit checks CRC-7 and reports the result to SD status register. When the data input enable bit of SD access control register is set, SDIO host controller waits for a block of data from a specific SD card. When a block of data is received, this bit is cleared to 0 automatically. - 235 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 The received block of data is stored into the system memory and the address is starting from the address specified by S/W. SDIO host controller checks the associated CRC-16 bits and reports the result to SD status register. If the data-input interrupt is enabled, an interrupt will occur when the data transfer is finished. The data input status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify a data-input interrupt by reading this bit. When the data output enable bit of SD access control register is set, SDIO host controller transfers a block of data to a specific MMC card. When the data transfer is finished, this bit is cleared to 0 automatically. Before the data is transferred, the data to be transmitted must be stored into system memory and the S/W must specified the starting address where the data is stored. SDIO host controller will generate the associated CRC-16 bits by itself. After the data is transmitted, it also check the CRC-status response from the SD card. The check result is stored into the SD status register. If the data-output interrupt is enabled, an interrupt will occur when the data transfer is finished. The data output status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify a data-output interrupt by reading this bit. 1. When the response R2 input enable bit of SD access control register is set, SDIO host controller transfers a block of data to a specific SD card. When the data transfer is finished and this bit is set, SDIO host controller will waits for a 136-bit R2 response from SD card. When the R2 response is completely received, the bit is reset to 0 automatically. The received data of R2 response token (136-bit) is stored into the system memory, starting from the address specified by software. SDIO host controller checks the CRC-7 and reports the result to SD status register. 2. When the 74-clock cycles output enable bit of SD access control register is set, SDIO host controller generates 74 clock cycles without any CMD or DAT activity. After the 74 clock cycles have been generated, the bit is reset to 0 automatically. - 236 - W90P710 7.9.2 Register Mapping ADDRESS R/W DESCRIPTION RESET VALUE REGISTER SDIO Registers (6) SDGCR 0xFFF0_0000 SDDSA SDBCR SDGIER SDGISR 0xFFF0_0004 0xFFF0_7008 0xFFF0_700C 0xFFF0_7010 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R SD Global Control Register SD DMA Transfer Starting Address Register SD DMA Byte Count Register SD Global Interrupt Enable Register SD Global Interrupt Status Register SD BIST Register SD Interface Control Register SD Host Interface Initial Register SD Interface Interrupt Enable Register SD Interface Interrupt Status Register SD Command Argument Register SD Receive Register 0 SD Receive Register 1 Response Response Token Token 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0018 0x0000_0000 0x0000_00XX 0x0000_0000 0xXXXX_XXXX 0x0000_XXXX 0x0000_0000 SDBIST 0xFFF0_7014 Secure Digital Registers (8) SDICR 0xFFF0_7300 SDHIIR SDIIER SDIISR SDAUG SDRSP0 SDRSP1 0xFFF0_7304 0xFFF0_7308 0xFFF0_730C 0xFFF0_7310 0xFFF0_7314 0x0000_0318 SDBLEN 0xFFF0_731C R/W SD Block Length Register Internal Buffer Access Register (256) 0xFFF0_7400 FB0_0 ..... ..... R/W Flash Buffer 0 FB0_127 0x0000_05FC FB1_0 ..... FB1_127 0xFFF0_7800 ..... 0x0000_09FC R/W Flash Buffer 1 Undefined Undefined - 237 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.9.3 SDIO Register Description SD Gloal Control Register (SDGCR) REGISTER ADDRESS 0xFFF0_7000 R/W DESCRIPTION RESET VALUE SDGCR 31 23 15 7 Reserved R/W 29 21 13 SD Glogal Control Register 0x0000_0000 25 17 9 RdSel 1 SWRST 24 16 8 0 SDIOEN 30 22 14 6 28 20 12 4 27 Reserved 19 Reserved 11 3 DMARd 26 18 10 2 DMAWr Reserved 5 WrSel BITS DESCRIPTIONS [31:11] Reserved Read Select This field indicates which of DMA or SDIO host controller can read data from buffer 0 or buffer 1. [10:8] RdSel 3'b000: DMA can read buffer 0 (Default) 3'b011: SDIO host controller can read buffer 0 3'b100: DMA can read buffer 1 3'b111: SDIO host controller can read buffer 1 Write Select This field indicates which of DMA, SDIO host controller can write data into buffer 0 or buffer 1. [6:4] WrSel 3'b000: DMA can write buffer 0 (Default) 3'b011: SDIO host controller can write buffer 0 3'b100: DMA can write buffer 1 3'b111: SDIO host controller can write buffer 1 - 238 - W90P710 Continued. BITS DESCRIPTIONS DMA Read Enable Set this bit high enables the DMA to transfer data from external SDRAM to internal buffer. This bit will be cleared automatically after DMA operation finished. Write 0 to this bit has no effect. 1'b0: No DMA operation (Default) 1'b1: Enable DMA read operation DMA Write Enable Set this bit high enables the DMA to transfer data from internal buffer into external SDRAM. This bit will be cleared automatically after DMA operation finished. Write 0 to this bit has no effect. 1'b0: No DMA operation (Default) 1'b1: Enable DMA write operation Software Reset [1] SWRST Set this bit high will reset only the logic circuit of SDIO host controller and has no effect on all control registers. 1'b0: No operation (Default) 1'b1: Enable software reset SDIO Function Enable SDIOEN Set this bit high enables the SDIO host controller operation. If this bit is cleared, all operations are disabled and SDIO host controller only responses to control register access. 1'b0: Disable SDIO host controller (Default) 1'b1: Enable SDIO host controller [3] DMARd [2] DMAWr [0] SD DMA Transfer Starting Address Register (SDDSA) REGISTER ADDRESS 0xFFF0_7004 R/W DESCRIPTION RESET VALUE SDDSA R/W SD DMA Transfer Starting Address Register 0x0000_0000 - 239 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 DMASA 20 DMASA 12 DMASA 4 DMASA 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS DMA Transfer Starting Address [31:0] DMASA This field defines the address of external SDRAM where DMA reads/writes data from/to. - 240 - W90P710 SD DMA Byte Count Register (SDBCR) REGISTER ADDRESS 0xFFF0_7008 R/W DESCRIPTION RESET VALUE SDBCR 31 23 15 7 R/W 29 21 13 5 SD DMA Byte Count Register 28 20 12 4 BCNT 27 19 11 3 26 18 10 2 25 17 9 BCNT 1 0x0000_0000 24 16 8 0 30 22 14 Reserved 6 Reserved Reserved BITS DESCRIPTIONS [31:12] Reserved DMA Transfer Byte Count [11:0] BCNT This field defines the byte count of DMA Transfer between internal flash buffer and external SDRAM. SD Global Interrupt Enable Register (SDGIIER) REGISTER ADDRESS 0xFFF0_70 0C R/W DESCRIPTION RESET VALUE SDGIER R/W SD Global Interrupt Enable Register 0x0000_0000 31 23 15 7 Reserved 30 22 14 6 ERRIEN 29 21 13 5 DRdIEN 27 Reserved 20 19 Reserved 12 4 DWrIEN 11 Reserved 3 SDHIIEN 28 26 18 10 2 Reserved 25 17 9 1 Reserved 24 16 8 0 SDIOGIEN - 241 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:7] [6] Reserved ERRIEN Bus Error Interrupt Enable DMA Read Interrupt Enable This bit controls the SDIO host controller interrupt generation from the interrupt of the DMA read operation. 1'b0: DMA read interrupt is masked from SDIO host controller interrupt generation 1'b1: DMA read interrupt can participate in SDIO host controller interrupt generation DMA Write Interrupt Enable This bit controls the SDIO host controller interrupt generation from the interrupt of the DMA write operation. 1'b0: DMA write interrupt is masked from SDIO host controller interrupt generation 1'b1: DMA write interrupt can participate in SDIO host controller interrupt generation Secure Digital Host Controller Interface Interrupt Enable This bit controls the SDIO host controller interrupt generation from the interrupt of Secure Digital host controller. 1'b0: Secure Digital host controller's interrupt is masked from SDIO host controller interrupt generation 1'b1: Secure Digital host controller's interrupt can participate in SDIO host controller interrupt generation SDIO Host Global Interrupt Enable [0] SDIOGIEN This bit controls the interrupt generation of SDIO host controller Globally. 1'b0: Disable SDIO host controller interrupt generation globally 1'b1: Enable SDIO host controller interrupt generation globally [5] DRdIEN [4] DWrIEN [3] SDHIIEN SD global Interrupt Status Register (SDGISR) REGISTER ADDRESS 0xFFF0_7010 R/W DESCRIPTION RESET VALUE SDGISR R/W SD Global Interrupt Status Register 0x0000_0000 - 242 - W90P710 31 23 15 7 Reserved 30 22 14 6 ERRINT 29 21 13 5 DRdINT 28 20 12 4 DWrINT 27 Reserved 19 Reserved 11 Reserved 3 SDHINT 26 18 10 2 Reserved 25 17 9 1 Reserved 24 16 8 0 SDIOGINT BITS DESCRIPTIONS [31:7] [6] Reserved ERRINT Bus Error Interrupt Status DMA Read Interrupt Status [5] DRdINT This bit indicates the DMA read transfer (from external SDRAM to internal buffer) has finished. 1'b0: No DMA read transfer completion 1'b1: DMA read transfer completed DMA Write Interrupt Status [4] DWrINT This bit indicates the DMA write transfer (from internal buffer to external SDRAM) has finished. 1'b0: No DMA write transfer completion 1'b1: DMA write transfer completed Secure Digital Host Controller Interface Interrupt Status [3] SDHIINT This bit indicates there is an interrupt status from Secure Digital host controller. 1'b0: No interrupt status from Secure Digital host controller interface. 1'b1: There is an interrupt status from Secure Digital host controller Interface SDIO Host Global Interrupt Status [0] SDIOGINT This bit is the wired-OR of SDHINT, DWrINT and DRdINT. 1'b0: No SDIO host controller interrupt notification 1'b1: There is an SDIO host controller interrupt status - 243 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 SDIO BIST Register (SDIOBIST) REGISTER ADDRESS 0xFFF0_7014 R/W DESCRIPTION RESET VALUE SDIOBIST 31 23 15 7 R/W 29 21 13 5 SDIO BIST Register 28 20 12 4 27 Reserved 19 Reserved 11 Reserved 3 BistFail 26 18 10 2 25 17 9 1 Finish 0x0000_0000 24 16 8 0 BISTEN 30 22 14 6 Reserved BITS DESCRIPTIONS [31:4] Reserved BIST Fail The BistFail indicates if the BIST test fails or succeeds. If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation. The BistFail is a write clear field. Write 1 to this field clears the content and write 0 has no effect. BIST Operation Finish [3:2] BistFail [1] Finish It indicates the end of the BIST operation. When BIST controller finishes all operations, this bit will be set high. This bit is a write clear field. Write 1 to this field clears the content and write 0 has no effect. BIST Enable The BISTEN is used to enable the BIST operation. If high enables the BIST controller to do embedded SRAM test. This bit is also used to do the reset for BIST circuit. It is necessary to reset the BIST circuit one clock cycle at least in order to initialize the BIST properly. The BISTEN can be disabled by write 0. [0] BISTEN - 244 - W90P710 SD Interface Control Register (SDCR) REGISTER ADDRESS 0xFFF0_7300 R/W DESCRIPTION RESET VALUE SDICR 31 23 15 SD_CS 7 CLK_KEEP R/W 29 21 13 5 SD Interface Control Register 0x0000_0000 26 18 10 2 25 17 9 1 RI_EN 24 16 8 0 CO_EN 30 22 14 Reserved 28 Reserved 20 Reserved 12 4 R2_EN 27 19 11 3 DO_EN CMD_CODE 74CLK_OE 6 8CLK_OE DI_EN BITS DESCRIPTIONS [31:16] Reserved SD Card Select Control 0=Select SD card-0 1=Select SD card-1 It is fixed to 0 at W99P710 [15] SD_CS [13:8] CMD_CODE SD Command Code This register contains the SD command code (00H - 3FH). SD Clock Enable [7] CLK_KEEP 0=Disable SD clock generation 1=SD clock always keeps free running. 8 Clock Cycles Output Enable 0=Disable [6] 8CLK_OE 1=Enable, SDIO host controller output 8 clock cycles When the operation is finished, this bit is automatically cleared to "0" by H/W circuit. - 245 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS 74 Clock Cycle Output Enable 0=Disable [5] 74CLK_OE 1=Enable, SDIO host controller outputs 74 clock cycles When the operation is finished, this bit is automatically cleared to "0" by H/W circuit. Response R2 Input Enable 0=Disable [4] R2_EN 1=Enable, SDIO host controller will wait to receive a response R2 from DS card and store the response data into flash buffer. When the R2 response operation is finished, this bit is automatically cleared to "0" by H/W circuit. Data Output Enable 0=Disable [3] DO_EN 1=Enable, SDIO host controller will transfer a single block data and the CRC-16 code to SD card. When the data output operation is finished, this bit is automatically cleared to "0" by H/W circuit. Data Input Enable 0=Disable [2] DI_EN 1=Enable, SDIO host controller will wait to receive a single block data and the CRC-16 code from SD card. When the data input operation is finished, this bit is automatically cleared to "0" by H/W circuit. Response Input Enable 0=Disable [1] RI_EN 1=Enable, SDIO host controller will wait to receive a response from SD card. When the response operation is finished, this bit is automatically cleared to "0" by H/W circuit. Command Output Enable 0=Disable [0] CO_EN 1=Enable, SDIO host controller will transfer a command to SD card. When the command operation is finished, this bit is automatically cleared to "0" by H/W circuit. - 246 - W90P710 SD Host interface Initial Register (SDHIIR) REGISTER ADDRESS 0xFFF0_7304 R/W DESCRIPTION RESET VALUE SDHIIR 31 23 15 7 R/W 29 21 13 5 SD Host Interface Initial Register 28 20 12 Reserved 4 SD_CLK 27 Reserved 19 Reserved 11 3 26 18 10 2 25 17 9 1 0x0000_0018 24 16 8 SPD 0 30 22 14 6 BITS DESCRIPTIONS [31:9] [8] Reserved SPD Data Bus Width Control 0=1-bit data bus 1=4-bit data bus SD Clock Control The frequency of SD clock will be equal to (Input Clock/(SD_CLK+1)). The SD_CLK = 8'h00 is reserved. [7:0] SD_CLK SD Interface Interrupt Enable Register (SDIIER) REGISTER ADDRESS 0xFFF0_7308 R/W DESCRIPTION RESET VALUE SDIIER 31 23 15 7 R/W SD Interface Interrupt Enable Register 28 20 12 4 SDIO_IEN 0x0000_0000 25 17 9 1 24 16 8 0 DI_IEN 30 22 14 6 Reserved 29 21 13 5 27 Reserved 19 Reserved 11 Reserved 3 DAT0_IEN 26 18 10 2 CD_IEN DO_IEN - 247 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:5] Reserved SDIO Interrupt Status Enable [4] SDIO_IEN 0=Disable SDIO_IS interrupt generation 1=Enable SDIO_IS interrupt generation SD DAT0 Level Transition Interrupt Status Enable [3] DAT0_IEN 0=Disable DAT0_STS interrupt generation 1=Enable DAT0_STS interrupt generation CD# Interrupt Status Enable [2] CD_IEN 0=Disable CD_IS interrupt generation 1=Enable CD_IS interrupt generation Data Output Interrupt Status Enable [1] DO_IEN 0=Disable DO_IS interrupt generation 1=Enable DO_IS interrupt generation Data Input Interrupt Status Enable [0] DI_IEN 0=Disable DI_IS interrupt generation 1=Enable DI_IS interrupt generation SD Interface Interrupt Status Register (SDIISR) Register SDISR 31 23 15 7 CD_ Address 0xFFF0_730C R/W R/W 29 21 13 Reserved 5 CRC Description SD Interface Interrupt Status Register 28 20 12 4 CRC-16 27 Reserved 19 Reserved 11 3 CRC-7 26 18 10 DAT1_IS_ Reset Value 0x0000_00XX 25 17 9 SD_DATA0 30 22 14 6 R2_CRC7 24 16 8 DAT0_STS 2 CD_IS 1 DO_IS 0 DI_IS - 248 - W90P710 BITS DESCRIPTIONS [31:11] Reserved SDIO Interrupt Value Status 0 = SDIO interrupt at interrupt period. Write 1 to clear this status bit (set DAT1_IS_ to 1). 1 = no SDIO interrupt at interrupt period. If SDIO_IEN is set and DAT1_IS_ is 0, an interrupt request will be generated. Interrupt period is defined: (1) (2) If SD data bus width is 1 and DAT[1] is unused, the interrupt period is any time on DAT[1] If SD data bus width is 4, the interrupt period is at the single clock that is 2 clocks after the End bit of data block [10] DAT1_IS_ [9] SD_DATA0 SD DAT0 Value SD Level Transition Status [8] DAT0_STS 0=No level transition 1=DAT0 value changes from high to low or low to high. Write 1 to clear this status bit. Card Detection Indicator Response R2 CRC-7 Check Status [6] R2_CRC7 0=Fault 1=OK CRC Check Result Status [5] CRC 0=Fault 1=OK CRC-16 Check Result Status [4] CRC-16 0=Fault 1=OK CRC-7 Check Result Status [3] CRC-7 0=Fault 1=OK [7] CD_ - 249 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS CD# Interrupt Status [2] CD_IS 0=No Interrupt Generated 1=Interrupt Generated Note: Write "1" into this bit will clear the interrupt status. Data Output Interrupt Status [1] DO_IS 0=No Interrupt Generated 1=Interrupt Generated Note: Write "1" into this bit will clear the interrupt status. Data Input Interrupt Status [0] DI_IS 0=No Interrupt Generated 1=Interrupt Generated Note: Write "1" into this bit will clear the interrupt status. SD Command Argument Register (SDAUG) REGISTER ADDRESS 0xFFF0_7310 R/W DESCRIPTION RESET VALUE SDARG 31 23 15 7 R/W 29 21 13 5 SD Command Argument Register 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 30 22 14 6 SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG BITS DESCRIPTIONS [31:0] SD_CMD_AR G SD Command Argument This register contains a 32-bit value specifies the argument of SD command from host controller to card. SD Receive Response Token Register 0 (SDRSP0) - 250 - W90P710 REGISTER ADDRESS 0xFFF0_7314 R/W DESCRIPTION RESET VALUE SDRSP0 31 23 15 7 R 29 21 13 5 SD Receive Response Token Register 0 28 20 12 27 19 11 26 18 10 2 25 17 9 1 0xXXXX_XXXX 24 16 8 0 30 22 14 6 SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 4 3 SD_RSP_TK0 BITS DESCRIPTIONS SD Receive Response Token 0 [31:0] SD_RDP_TK0 SD host controller will receive a response token for getting a reply from SD card. This register records the bit 47-16 of the response token. SD Receive Response Token Register 1 (SDRSP1) REGISTER ADDRESS 0xFFF0_7318 R/W DESCRIPTION RESET VALUE SDRSP1 31 23 15 7 R 29 21 13 5 SD Receive Response Token Register 1 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_XXXX 24 16 8 0 30 22 14 6 Reserved Reserved Reserved SD_RSP_TK1 - 251 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:8] Reserved SD Receive Response Token 1 [7:0] SD_RSP_TK1 SD host controller will receive a response token for getting a reply from SD card. This register records the bit 15-8 of the response token. SD Block Length Register (SDBLEN) REGISTER ADDRESS 0xFFF0_731C R/W DESCRIPTION RESET VALUE SDBLEN 31 23 15 7 R/W 29 21 13 5 SD Block Length Register 28 20 12 Reserved 4 27 Reserved 19 Reserved 11 3 SDBLEN DESCRIPTIONS 0x0000_0000 26 18 10 2 25 17 9 1 24 16 8 SDBLEN 0 30 22 14 6 BITS [31:9] [8:0] Reserved SDBLEN SD BLOCK LENGTH A 9-bit value specifies the SD transfer byte count. Flash Buffer 0 Registers (FB0_0 ~ FB0_127) REGISTER ADDRESS 0xFFF0_7400 ..... 0xFFF0_75FC R/W DESCRIPTION RESET VALUE FB0_0 ..... FB0_127 31 R/W Flash Buffer 0 Undefined 30 29 28 27 26 25 24 - 252 - W90P710 FBuf0 23 15 7 22 14 6 21 13 5 20 FBuf0 12 FBuf0 4 FBuf0 BITS DESCRIPTIONS 19 11 3 18 10 2 17 9 1 16 8 0 Flash Buffer 0 [31:0] FBuf0 These register ports supports the data read from embedded flash buffer 0. The embedded flash buffer size is 512 bytes, the 128 words. Consequently, the address range for flash buffer 0 is from 0xFFF0_7400 to 0xFFF0_75FC. Flash Buffer 1 Registers (FB1_0 ~ FB1_127) REGISTER ADDRESS 0xFFF0_7800 ..... 0xFFF0_79FC R/W DESCRIPTION RESET VALUE FB1_0 ..... FB1_127 31 23 15 7 R/W Flash Buffer 1 Undefined 30 22 14 6 29 21 13 5 28 FBuf1 20 FBuf1 12 FBuf1 4 FBuf1 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] FBuf1 Flash Buffer 1 These register ports supports the data read from embedded flash buffer 1. The embedded flash buffer size is 512 bytes, the 128 words. Consequently, the address range for flash buffer 1 is from 0xFFF0_7800 to 0xFFF0_79FC. - 253 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.10 LCD Controller 7.10.1 Main Features STN LCD Display Supports Sync-type STN LCD Supports 2 types of LCD panels: 4-bit single scan and 8-bit single scan display type Supports 16 gray levels for Monochrome STN LCD panel Supports 4096(12bpp) color for Color STN LCD panel Virtual coloring method: Frame Rate Control (16-level) Anti-flickering method: Time-based Dithering TFT LCD Display Supports Sync-type TFT LCD and Sync-type High-color TFT LCD Supports 1, 2, 4 or 8-bpp palette color display Supports 12-bpp/16-bpp/18-bpp/24-bpp non-palette true color display TV Encoder Supports 8-bit YCbCr data output format to connect with external TV Encoder LCD Preprocessing Image re-size - Horizontal/Vertical Down-Scaling - Horizontal/Vertical Up-Scaling Image relocation - Horizontal /Vertical Cropping - Virtual Display LCD Post processing Support for one OSD overlay Support various OSD function Others Color-look up table size 256x32 bit for TFT used Dedicated DMA for block transfer mode Supports image which is RGB formats or YUV422 formats. - 254 - W90P710 7.10.2 LCD Register MAP REGISTER NAME DESCRIPTION R/W ADDRESS LCD Controller LCDCON LCD Interrupt Control LCDINTENB LCDINTS LCDINTC LCD Pre-processing OSDUPSCF VDUPSCF OSDDNSCF VDDNSCF LCD FIFO Control FIFOCON FIFOSTATUS FIFO1PRM FIFO2PRM FIFO1SADDR FIFO2SADDR FIFO1DREQCNT FIFO2DREQCNT FIFO1CURADR FIFO2CURADR FIFO1RELACOLCNT FIFO2RELACOLCNT Color Generation LUTENTRY1 LUTENTRY2 LUTENTRY3 LUTENTRY4 TFT: lookup table entry index register TFT: lookup table entry index register TFT: lookup table entry index register TFT: lookup table entry index register Read/Write Read/Write Read/Write Read/Write 0xFFF0_8060 0xFFF0_8064 0xFFF0_8068 0xFFF0_806C FIFOs control register FIFOs status FIFO1 parameters FIFO2 parameters FIFO1 transfer start address register FIFO2 transfer start address register FIFO1 data request transfer count register FIFO2 data request transfer count register FIFO1 current access address FIFO2 current access address FIFO1 real column count register FIFO2 real column count register Read/Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Read Read/Write Read/Write 0xFFF0_8020 0xFFF0_8024 0xFFF0_8028 0xFFF0_802C 0xFFF0_8030 0xFFF0_8034 0xFFF0_8038 0xFFF0_803C 0xFFF0_8040 0xFFF0_8044 0xFFF0_8048 0xFFF0_804C OSD data Horizontal/Vertical scaling factor Video data Horizontal/Vertical upscaling factor OSD data Horizontal/Vertical downscaling factor Video data Horizontal/Vertical downscaling factor upRead/Write Read/Write Read/Write Read/Write 0xFFF0_8010 0xFFF0_8014 0xFFF0_8018 0xFFF0_801C LCD interrupt enable register LCD interrupt status register LCD interrupt clear Register Read/Write Read Write 0xFFF0_8004 0xFFF0_8008 0xFFF0_800C LCD Controller control register Read/Write 0xFFF0_8000 - 255 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. REGISTER NAME Color Generation DESCRIPTION Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern R/W ADDRESS TMDDITHP1 TMDDITHP2 TMDDITHP3 TMDDITHP4 TMDDITHP5 TMDDITHP6 TMDDITHP7 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read 0xFFF0_8070 0xFFF0_8074 0xFFF0_8078 0xFFF0_807C 0xFFF0_8080 0xFFF0_8084 088 0xFFF0_8090 0xFFF0_8094 0xFFF0_8098 0xFFF0_809C 0xFFF0_80A0 0xFFF0_80A4 0xFFF0_80A8 0xFFF0_80AC 0xFFF0_80B0 0xFFF0_80B4 0xFFF0_80B8 0xFFF0_80BC 0xFFF0_80C0 0xFFF0_80C4 LCD Post-processing DDISPCP Dummy Display Color Pattern Register Valid Display Window Starting VDISPWINS Coordinate Register Valid Display Window Ending VDISPWINE Coordinate Register OSD Window Starting Coordinate OSDWINS Register OSD Window Ending Coordinate OSDWINE Register OSDOVCN OSD Overlay Control Register OSDKYP OSD Overlay Color-Key Pattern OSDKYM OSD Overlay Color-Key Mask LCD Timing Generation LCDTCON1 LCDTCON2 LCDTCON3 LCDTCON4 LCDTCON5 LCDTCON6 LCD Timing Control Register1 LCD Timing Control Register2 LCD Timing Control Register3 LCD Timing Control Register4 LCD Timing Control Register5 LCD Timing Control Register6 Palette SRAM Build In Self Test Register LCD SRAM Build In Self Test BIST Look Up Table SRAM 0xFFF0_0100 Read/Write ... 0xFFF0_84FF Read/Write 0xFFF0_80D0 - 256 - W90P710 7.10.3 LCD Special Register Description 7.10.3.1. LCD Controller LCD Controller Control Register (LCDCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDCON 0xFFF0_8000 R/W LCD Controller control register 0x0000_0000 31 23 15 7 TVEN 30 22 Reserved 14 Reserved 6 LCDMON8 29 Reserved 21 13 5 TFTTYPE 28 20 YUV_nRGB 12 YUV_SEQ 4 LCDTFT 27 19 OSDEN 11 3 LCDBW 26 18 LUTWREN 10 RGBSEQ 2 25 PPRST 17 LUTEN 9 24 LCDRST 16 LCDCEN 8 LCDBUS 0 1 LCDBPP BITS DESCRIPTIONS [31:26] Reserved Reserved LCD Pre-Processor Reset [25] PPRST 0 = Disable, normal operation 1 = Only reset the LCD Pre-Processor, clear FIFO, AHB protocol restart. LCD Controller Reset(except Control Registers) 0 = Disable, normal operation 1 = Reset the whole LCD Controller include LCD Timing Generator Reserved Image stored in memory device is YUV format or RGB format 0 = RGB format 1 = YUV format If this bit is set to 1, LCDBPP must be set to 101 ( 16bpp ) OSD Data Fetch Control 0 = Disable 1 = Enable [24] [23:21] LCDRST Reserved [20] YUV_nRGB [19] OSDEN - 257 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [18] LUTWREN Look Up Table SRAM Read/Write Enable 0 = Disable 1 = Enable Look Up Table Enable 0 = Disable 1 = Enable LCD Controller Enable 0 = Disable VSYNC, HSYNC, VCLK, VD, and VDEN 1 = Enable VSYNC, HSYNC, VCLK, VD, and VDEN Reserved YUV output sequence( only used at TV-Encoder) 00 = UYVY [17] LUTEN [16] [15:14] LCDCEN Reserved [13:12] YUV_SEQ 01 = YUYV 10 = VYUY 11 = YVYU LCD Line Data Sequence( only used at Sync-Type non High Color TFT) [11:10] RGBSEQ 00 = First line data is RGB, second line data is GBR 01 = First line data is BGR, second line data is RBG 10 = First line data is GBR, second line data is RGB 11 = First line data is RBG, second line data is BGR Video Data output re-map( Only used at Sync-type High Color TFT) [9:8] LCDBUS 00 = Data bus is 24bit 01 = Data bus is 18bit 10 = Data bus is 8bit [7] TVEN External TV encoder Enable 0 = Normal operation 1 = Convert RGB to YCbCr for external TV encoder Monochrome LCD has an 8-bit interface 0 = mono LCD use 4-bit interface 1 = mono LCD uses 8-bit interface [6] LCDMON8 - 258 - W90P710 Continued. BITS DESCRIPTIONS TFT Type Select [5] TFTTYPE 0 = Sync-type High Color TFT LCD 1 = Sync-type TFT LCD [4] LCDTFT LCD is TFT 0 = LCD is a STN display 1 = LCD is a TFT display STN LCD is monochrome 0 = STN LCD is color 1 = STN LCD is monochrome LCD bits per pixel 011 = 8 bpp RGB332 100 = 12 bpp RGB444 101 = 16 bpp RGB565 110 = 18 bpp RGB666 [3] LCDBW [2:0] LCDBPP NOTE: LCDBPP means the resolution (Bit Per-Pixel) of the image data which store in memory device. If LUTEN is enabled, LCD Controller will output data from Palette SRAM for 8bpp image. Else, LCD Controller will treat 8bpp data as RGB332. At normally, Video Data bus output is RGB888, 24bit. If LCDBUS is set to 01, Video Data bus output is RGB666, 18bit. If LCDBUS is set to 10, Video Data bus output is RGB332, 8bit. The other bit will be replaced with zero. Please refer to GPIO chapter to setting this register. 7.10.3.2. LCD Interrupt Control There are enable register, clear register, status register for every interrupt type. Enable Mask set/clear register will branch firmware into interrupt sub-routine. Firmware can read Status register to identify which interrupt generate now. Write Clear register will clear the interrupt status. Status register will be set even if firmware disable the Enable register. Main-routine can read Status register and write Clear register. LCD Interrupt Enable Register (LCDINTENB) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDINTENB 0xFFFF0_0004 R/W LCD interrupt enable register 0x0000_0000 - 259 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 Reserved 13 5 HSEN 28 20 12 4 VSEN 27 Reserved 19 11 Reserved 3 VLFINEN2 26 18 UNDREN2 10 2 VFFINEN2 25 17 UNDREN1 9 1 VLFINEN1 24 16 AHBEREN 8 0 VFFINEN1 Reserved BITS DESCRIPTIONS [31:19] [18] [17] [16] [15:6] [5] [4] [3] [2] [1] [0] Reserved UNDREN2 UNDREN1 AHBEREN Reserved HSEN VSEN VLFINEN2 VFFINEN2 VLFINEN1 VFFINEN1 Reserved FIFO2 UNDERRUN interrupt enable FIFO1 UNDERRUN interrupt enable AHB ERROR interrupt enable Reserved HSYNC interrupt enable VSYNC interrupt enable FIFO2 VLINE FINISH interrupt enable FIFO2 VFRAME FINISH interrupt enable FIFO1 VLINE FINISH interrupt enable FIFO1 VFRAME FINISH interrupt enable LCD Interrupt Status Register (LCDINTS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDINTS 0xFFF0_8008 R LCD interrupt status register 0x0000_0000 - 260 - W90P710 31 23 15 7 30 22 14 6 29 21 Reserved 13 5 HSIS 28 20 12 4 VSIS 27 Reserved 19 11 Reserved 3 VLFINIS2 26 18 UNDRIS2 10 2 VFFINIS2 25 17 UNDRIS1 9 1 VLFINIS1 24 16 AHBERIS 8 0 VFFINIS1 Reserved BITS DESCRIPTIONS [31:20] [18] [17] [16] [15:6] [5] [4] [3] [2] [1] [0] Reserved UNDRIS2 UNDRIS1 AHBERIS Reserved HSIS VSIS VLFINIS2 VFFINIS2 VLFINIS1 VFFINIS1 Reserved FIFO2 have no data for output to Panel FIFO1 have no data for output to Panel AHB master bus error status Reserved Timing Generator output a HSYNC pulse Timing Generator output a VSYNC pulse FIFO2 transfer one line stream complete FIFO2 transfer one frame stream complete FIFO1 transfer one line stream complete FIFO1 transfer one frame stream complete - 261 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 LCD Controller is an AHB Master at AMBA and fetching video data from an AHB Slave such as SDRAM or FLASH memory. If AHB Slave response ERROR for LCD Controller's data request, AHBERIS will be set. If the data rate of output to LCD Panel is too fast and the data rate of fetch data from AMBA is too slow; there are no data in FIFO for LCD Panel's request, UNDRISx will be set. LCD Timing Generation register need to be re-configured. HSIS and VSIS provide information for firmware to know the status of LCD Panel. VLFINISx and VFFINISx provide information for firmware to know how much data FIFO have fetched. LCD Interrupt Clear Register (LCDINTC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDINTC 0xFFF0_800C W LCD interrupt clear register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 Reserved 13 5 HSIC 28 20 12 4 VSIC 27 Reserved 19 11 Reserved 3 VLFINIC2 26 18 UNDRIC2 10 2 VFFINIC2 25 17 UNDRIC1 9 1 VLFINIC1 24 16 AHBERIC 8 0 VFFINIC1 Reserved BITS DESCRIPTIONS [31:20] [18] [17] [16] [15:6] [5] [4] Reserved UNDRIC2 UNDRIC1 AHBERIC Reserved HSIC VSIC Reserved Clear FIFO2 UNDERRUN interrupt Clear FIFO1 UNDERRUN interrupt Clear MBERROR interrupt Reserved Clear HSYNC interrupt Clear VSYNC interrupt - 262 - W90P710 Continued. BITS DESCRIPTIONS [3] [2] [1] [0] 7.10.3.3. VLFINIC2 VFFINIC2 VLFINIC1 VFFINIC1 Clear FIFO2 VLINEFINSH interrupt Clear FIFO2 VFRAMFINSH interrupt Clear FIFO1 VLINEFINSH interrupt Clear FIFO1 VFRAMFINSH interrupt LCD Pre-processing OSD Up-Scaling Factor Register (OSDUPSCF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDUPSCF 0xFFF0_8010 R/W OSD data Horizontal/Vertical up-scaling 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 20 12 4 27 Reserved 19 Reserved 11 Reserved 3 26 18 10 2 25 17 9 1 OSDVUP 24 16 8 0 Reserved OSDHUP BITS DESCRIPTIONS [31:5] Reserved Reserved OSD Stream Horizontal Up-scaling 00=1x 01=2x 10=4x OSD Stream Vertical Up-scaling 00=1x 01=2x 10=4x Reserved [4:3] OSDHUP [2:1] OSDVUP [0] Reserved - 263 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Video Up-Scaling Factor Register (VDUPSCF) Register VDUPSCF Address 0xFFF0_8014 R/W R/W Description Video data Horizontal/Vertical up-scaling Reset Value 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 20 12 4 VDHUP 27 Reserved 19 Reserved 11 Reserved 3 26 18 10 2 VDVUP 25 17 9 1 24 16 8 0 Reserved BITS DESCRIPTIONS [31:5] Reserved Reserved Video Horizontal Up-scaling control 00=1x 01=2x 10=4x Video Vertical Up-scaling control 00=1x 01=2x 10=4x Reserved [4:3] VDHUP [2:1] VDVUP [0] Reserved OSD Down-Scaling Factor Register (OSDDNSCF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDDNSCF 0xFFF0_8018 R/W OSD data Horizontal/Vertical down- 0x0000_0000 - 264 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 OSDVDNN OSDVDNM OSDHDNN OSDHDNM BITS DESCRIPTIONS [31:24] [23:16] [15:8] [7:0] OSDVDNN OSDVDNM OSDHDNN OSDHDNM An 8-bit value specifies the numerator part (N) of the vertical downscaling factor. An 8-bit value specifies the numerator part (M) of the vertical downscaling factor. An 8-bit value specifies the numerator part (N) of the Horizontal down-scaling factor. An 8-bit value specifies the numerator part (M) of the Horizontal down-scaling factor. Video Down-Scaling Factor Register (VDDNSCF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE VDDNSCF 0xFFF0_801C R/W Video data scaling factor Horizontal/Vertical down- 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 VDVDNN 20 VDVDNM 12 VDHDNN 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 VDHDNM - 265 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:24] [23:16] [15:8] [7:0] VDVDNN VDVDNM VDHDNN VDHDNM An 8-bit value specifies the numerator part (N) of the vertical downscaling factor. An 8-bit value specifies the numerator part (M) of the vertical downscaling factor. An 8-bit value specifies the numerator part (N) of the Horizontal down-scaling factor. An 8-bit value specifies the numerator part (M) of the Horizontal down-scaling factor. Up-Scaling or Down-Scaling, firmware can choose only one function of it. If both factor register is configured, the behavior of LCD Controller is undefined. 7.10.3.4. LCD FIFOs Controller LCD FIFO Control Register (FIFOCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFOCON 31 23 15 7 0xFFF0_8020 30 22 Reserved 14 6 13 5 29 21 R/W 28 20 12 4 Reserved LCD FIFOs controller register 27 Reserved 19 BPP24SW 11 Reserved 3 2 1 18 BPP18SW 10 17 26 25 0x0000_0000 24 16 BSWP 8 0 FIFOEN HSWP 9 Bits [31:20] [19] Descriptions Reserved BPP24SW Reserved FIFO 24bpp image swap control bit 0=Swap Disable 1=Swap Enable - 266 - W90P710 Continued. BITS DESCRIPTIONS [18] BPP18SW FIFO 18bpp image swap control bit 0=Swap Disable 1=Swap Enable FIFO half-word swap control bit. 0 = Swap Disable 1 = Swap Enable FIFO byte swap control bit. 0 = Swap Disable 1 = Swap Enable Reserved FIFOs transfer data enable x1 = FIFO1 transfer enable x0=FIFO1 transfer disable 1x = FIFO2 transfer enable 0x=FIFO2 transfer disable [17] HSWP [16] [15:2] [1:0] BSWP Reserved FIFOEN LCD FIFO Status Register (FIFOSTATUS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFOSTATUS 0xFFF0_8024 R LCD FIFOs status register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 20 12 4 27 Reserved 19 Reserved 11 Reserved 3 26 18 10 2 25 17 9 1 24 16 8 0 MASTERID BITS DESCRIPTIONS [31:2] [1:0] Reserved MASTERID Reserved Currently, the data bus master 01 = FIFO1 grant the bus 11 = FIFO2 grant the bus - 267 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 LCD FIFO1 Parameter Register (FIFO1PRM) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO1PRM 0xFFF0_8028 R/W LCD FIFO1 transfer parameters 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 20 12 Reserved 4 F1LOCK 27 F1STRIDE 19 F1STRIDE 11 3 26 18 10 2 25 17 9 1 24 16 8 0 F1BURSTY F1TRANSZ BITS DESCRIPTIONS [31:16] [15:5] [4] F1STRIDE Reserved F1LOCK Video frame buffer stride 16-bit value specifies the word offset of memory address of vertically adjacent line for FIFO1 fetching. Reserved FIFO1 lock transfer enable 0 = Disable 1 = Enable FIFO1 burst transfer type 00 =4 data burst mode 01 =8 data burst mode 10 =16 data burst mode FIFO1 data width per-transfer 00=one byte 01=half word 10=one word [3:2] F1BURSTY [1:0] F1TRANSZ LCD FIFO2 Parameter Register (FIFO2PRM) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO2PRM 0xFFF0_802C R/W LCD FIFO2 transfer parameters 0x0000_0000 - 268 - W90P710 31 23 15 7 30 22 14 6 Reserved BITS 29 21 13 5 28 20 12 4 F2LOCK 27 F2STRIDE 19 F2STRIDE 11 Reserved 3 26 18 10 2 25 17 9 1 24 16 8 0 F2BURSTY DESCRIPTIONS F2TRANSZ [31:16] [15:5] [4] F2STRIDE Reserved F2LOCK Video frame buffer stride 16-bit value specifies the word offset of memory address of vertically adjacent line for FIFO2 fetching. Reserved FIFO2 lock transfer enable 0 = Disable 1 = Enable FIFO2 burst transfer type 00 =4 data burst mode 01 =8 data burst mode 10 =16 data burst mode FIFO2 data width per-transfer 00=one byte 01=half word 10=one word [3:2] F2BURSTY [1:0] F2TRANSZ LCD FIFO1 Transfer Data Source Start Address Register (FIFO1SADDR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO1SADDR 31 23 15 7 0xFFF0_8030 30 22 14 6 R/W 29 21 13 5 FIFO1 transfer data source start address 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 FIFO1SADDR FIFO1SADDR FIFO1SADDR FIFO1SADDR - 269 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:0] FIFO1SADDR These bits indicate the source address of the bank location for the LCD frame buffer in the system memory. LCD FIFO2 Transfer Data Source Start Address Register (FIFO2SADDR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO2SADDR 31 23 15 7 0xFFF0_8034 30 22 14 6 29 21 13 5 R/W FIFO2 transfer data source start address 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 FIFO2SADDR FIFO2SADDR FIFO2SADDR FIFO2SADDR BITS DESCRIPTIONS [31:0] FIFO2SADDR These bits indicate the source address of the bank location for the LCD frame buffer in the system memory. LCD FIFO1 Data Request Transfer Count Register (FIFO1DREQCNT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO1DREQCNT 31 23 15 7 30 22 14 6 0xFFF0_8038 29 21 13 5 R/W 28 20 12 4 FIFO1 transfer data count register 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 FIFO1COLCNT FIFO1COLCNT FIFO1ROWCNT FIFO1ROWCNT - 270 - W90P710 BITS DESCRIPTIONS [31:16] [15:0] FIFO1COLCNT FIFO1ROWCNT These bits indicate the FIFO1 request count per-line of video These bits indicate the FIFO1 request count per-frame of video LCD FIFO2 Data Request Transfer Count Register (FIFO2DREQCNT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO2DREQCNT 0xFFF0_803C R/W FIFO2 transfer data count register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 FIFO2COLCNT FIFO2COLCNT FIFO2ROWCNT FIFO2ROWCNT BITS DESCRIPTIONS [31:16] [15:0] FIFO2COLCNT FIFO2ROWCNT These bits indicate the FIFO2 request count per-line of video These bits indicate the FIFO2 request count per-frame of video LCD FIFO1 Current Access Data Address Register (FIFO1CURADR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO1CURADR 0xFFF0_8040 R FIFO1 current access data address register 0x0000_0000 - 271 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 FIFO1CURADR FIFO1CURADR FIFO1CURADR FIFO1CURADR BITS DESCRIPTIONS [31:0] FIFO1CURADR Contains the approximate current FIFO1 access data address LCD FIFO2 Current Access Data Address Register (FIFO2CURADR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO2CURADR 0xFFF0_8044 R FIFO2 current access data address register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 FIFO2CURADR FIFO2CURADR FIFO2CURADR FIFO2CURADR BITS DESCRIPTIONS [31:0] FIFO2CURADR Contains the approximate current FIFO2 access data address - 272 - W90P710 LCD FIFO1 Real Column Count Register (FIFO1REALCULCNT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO1REALCULCNT 0xFFF0_8048 R/W FIFO1 real column count register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 Reserved 19 Reserved 11 3 26 18 10 2 25 17 9 1 24 16 8 0 FIFO1REALCOLCNT FIFO1REALCOLCNT BITS DESCRIPTIONS [31:16] [15:0] Reserved FIFO1REALCOLCN T Reserved These bits indicate the FIFO1 real column count per-frame of video LCD FIFO2 Real Column Count Register (FIFO2REALCULCNT) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO2REALCULCNT 0xFFF0_804C R/W FIFO2 real column count register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 FIFO2REALCOLCNT FIFO2REALCOLCNT - 273 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:16] [15:0] Reserved FIFO2REALCOLCNT Reserved These bits indicate the FIFO2 real column count per-line of video 7.10.3.5. Color Generation If the image is 8bpp (256 color) but connect to an 18bpp or higher resolution TFT-LCD Panel, Lookup Table can convert dull color become colorful. Take 8bpp image as example, there are still 256 colors but Lookup Table can convert a normal red to scarlet, claret, sienna or crimson. TFT Lookup Table Entry Index Register 1 (LUTENTRY1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LUTENTRY1 0xFFF0_8060 R/W TFT: lookup table entry index register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 LUTENTRY1 19 LUTENTRY1 11 LUTENTRY1 3 LUTENTRY1 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:0] LUTENTRY1 Theses bits define address of Palette SRAM when pixel data is 00 = LUTENTRY1[7:0] 01 = LUTENTRY1[15:8] 10 = LUTENTRY1[23:16] 11 = LUTENTRY1[31:24] - 274 - W90P710 TFT Lookup Table Entry Index Register 2 (LUTENTRY2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LUTENTRY2 0xFFF0_8064 R/W TFT: lookup table entry index register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 LUTENTRY2 LUTENTRY2 LUTENTRY2 LUTENTRY2 BITS DESCRIPTIONS [31:0] LUTENTRY2 Theses bits define address of Palette SRAM when pixel data is 00 = LUTENTRY2[7:0] 01 = LUTENTRY2[15:8] 10 = LUTENTRY2[23:16] 11 = LUTENTRY2[31:24] TFT Lookup Table Entry Index Register 3 (LUTENTRY3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LUTENTRY3 0xFFF0_8068 R/W TFT: lookup table entry index register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 LUTENTRY3 LUTENTRY3 LUTENTRY3 LUTENTRY3 - 275 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:0] LUTENTRY3 Theses bits define address of Palette SRAM when pixel data is 00 = LUTENTRY3[7:0] 01 = LUTENTRY3[15:8] 10 = LUTENTRY3[23:16] 11 = LUTENTRY3[31:24] TFT Lookup Table Entry Index Register 4 (LUTENTRY4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LUTENTRY4 0xFFF0_806C R/W TFT: lookup table entry index register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 LUTENTRY4 LUTENTRY4 LUTENTRY4 LUTENTRY4 BITS DESCRIPTIONS [31:0] LUTENTRY4 Theses bits define address of Palette SRAM when pixel data is 00 = LUTENTRY4[7:0] 01 = LUTENTRY4[15:8] 10 = LUTENTRY4[23:16] 11 = LUTENTRY4[31:24] TMED Dithering Pattern Register 1 (TMDDITHP1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP1 0xFFF0_8070 R/W Gray level dithered data duty pattern 0x0101_0001 - 276 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 DP2_16 20 DP2_16 12 DP1_16 4 DP1_16 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] DP2_16 DP1_16 Recommended pattern value for "4'b0010" gray level 0000 0001 0000 0001 Recommended pattern value for "4'b0001" gray level 0000 0000 0000 0001 TMED Dithering Pattern Register 2 (TMDDITHP2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP2 31 23 15 7 0xFFF0_8074 30 22 14 6 29 21 13 5 R/W Gray level dithered data duty pattern 28 DP4_16 20 DP4_16 12 DP3_16 4 DP3_16 3 2 1 11 10 9 19 18 17 27 26 25 0x1111_0841 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] DP4_16 DP3_16 Recommended pattern value for "4'b0100" gray level 0001 0001 0001 0001 Recommended pattern value for "4'b0011" gray level 0000 1000 0100 0001 - 277 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 TMED Dithering Pattern Register 3 (TMDDITHP3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP3 0xFFF0_8078 R/W Gray level dithered data duty pattern 0x4949_2491 31 23 15 7 30 22 14 6 29 21 13 5 28 DP6_16 20 DP6_16 12 DP5_16 4 DP5_16 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] DP6_16 DP5_16 Recommended pattern value "4''b0110" gray level 0100 1001 0100 1001 Recommended pattern value "4''b0101" gray level 0010 0100 1001 0001 TMED Dithering Pattern Register 4 (TMDDITHP4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP4 0xFFF0_807C R/W Gray level dithered data duty pattern 0x5555_52A5 31 23 15 7 30 22 14 6 29 21 13 5 28 DP8_16 20 DP8_16 12 DP7_16 4 DP7_16 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - 278 - W90P710 BITS DESCRIPTIONS [31:16] [15:0] DP8_16 DP7_16 Recommended pattern value "4''b1000" gray level 0101 0101 0101 0101 Recommended pattern value "4''b0111" gray level 0101 0010 1010 1001 TMED Dithering Pattern Register 5 (TMDDITHP5) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP5 0xFFF0_8080 R/W Gray level dithered data duty pattern 0xB6B6_B556 31 23 15 7 30 22 14 6 29 21 13 5 28 DP10_16 20 DP10_16 12 DP9_16 4 DP9_16 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] DP10_16 DP9_16 Recommended pattern value "4''b1010" gray level 1011 0110 1011 0110 Recommended pattern value "4''b1001" gray level 1011 0101 0101 0110 TMED Dithering Pattern Register 6 (TMDDITHP6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP6 0xFFF0_8084 R/W Gray level dithered data duty pattern 0xEEEE_DB6E - 279 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 DP12_16 20 DP12_16 12 DP11_16 4 DP11_16 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] DP12_16 DP11_16 Recommended pattern value "4''b1100" gray level 1110 1110 1110 1110 Recommended pattern value "4''b1011" gray level 1101 1011 0110 1110 TMED Dithering Pattern Register 7 (TMDDITHP7) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TMDDITHP7 0xFFF0_8088 R/W Gray level dithered data duty pattern 0xFEFE_EFBE 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 DP14_16 19 DP14_16 11 DP13_16 3 DP13_16 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] DP14_16 DP13_16 Recommended pattern value "4''b1110" gray level 1111 1110 1111 1110 Recommended pattern value "4''b1101" gray level 1110 1111 1011 1110 - 280 - W90P710 TFT palette color format BIT NAME DESCRIPTION 31:24 23:16 15:8 7:0 R[7:0] G[7:0] B[7:0] Reserved Red Palette data Green Palette data Blue Palette data STN 16-leve gray number & relative Time-based dithering Frame No Duty Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Probabilit y 9/1 6 7/1 6 8/1 6 7/1 6 8/1 7 7/1 6 8/1 6 7/1 6 8/1 6 7/1 6 8/1 6 7/1 6 8/1 6 7/1 6 8/1 6 7/1 6 #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 #16 Symbol " " instead of pixel turn-on, other is turn-off. - 281 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.10.3.6. LCD Post-processing Dummy Display Color Pattern Register (DDISPCP) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE DDISPCP 0xFFF0_8090 R/W Dummy Display Color Pattern Register 0x0000_0000 31 Reserved 23 15 7 30 22 14 6 29 21 13 5 28 20 DDISPR 12 DDISPG 4 DDISPB 27 GRAY 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31] [30:24] [23:16] [15:8] [7:0] Reserved GRAY DDISPR DDISPG DDISPB Reserved Replenish bit for 8bpp when LUTEN is disable LCD dummy display data of R component LCD dummy display data of G component LCD dummy display data of B component Video Display Windows Starting Coordinate Register (VDISPWINS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE VDISPWINS 0xFFF0_8094 R/W Valid Display Window Starting Coordinate 0x0000_0000 - 282 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 VDISPWYS VDISPWYS VDISPWXS VDISPWXS BITS DESCRIPTIONS [31:16] VDISPWYS Video Display Window Y-Start A 16-bit value specifies the vertical starting pixel positions of the LCD display window. Video Display Window X-Start A 16-bit value specifies the horizontal starting pixel positions of the LCD display window. [15:0] VDISPWXS Video Display Windows Ending Coordinate Register (VDISPWINE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE VDISPWINE 0xFFF0_8098 R/W Valid Display Window Ending Coordinate 0x0000_0000 31 30 29 28 27 26 25 24 VDISPWYE 23 15 7 22 14 6 21 13 5 20 12 4 19 11 3 18 10 2 17 9 1 16 8 0 VDISPWYE VDISPWXE VDISPWXE - 283 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:16] VDISPWYE Valid Display Window Y-End A 16-bit value specifies the vertical last pixel positions of the LCD display window. Valid Display Window X-End A 16-bit value specifies the horizontal last pixel positions of the LCD display window. [15:0] VDISPWXE OSD Windows Starting Coordinate Register (OSDWINS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDWINS 0xFFF0_809C R/W OSD Window Starting Coordinate 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 OSDWYS 19 OSDWYS 11 OSDWXS 3 OSDWXS 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] OSDWYS OSD Window Y-Start A 16-bit value specifies the vertical starting pixel positions of the OSD window. OSD Window X-Start A 16-bit value specifies the horizontal starting pixel positions of the OSD window. [15:0] OSDWXS OSD Windows Ending Coordinate Register (OSDWINE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDWINE 0xFFF0_80A0 R/W OSD Window Ending Coordinate 0x0000_0000 - 284 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 OSDWXE 26 18 10 2 25 17 9 1 24 16 8 0 OSDWYE OSDWYE OSDWXE BITS DESCRIPTIONS [31:16] OSDWYE OSD Window Y-End A 16-bit value specifies the vertical last pixel positions of the OSD window. OSD Window X-End A 16-bit value specifies the horizontal last pixel positions of the OSD window. [15:0] OSDWXE OSD Overlay Control Register (OSDOVCN) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDOVCN 0xFFF0_80A4 R/W OSD Overlay Control Register 0x0000_0000 31 23 15 7 Reserved 30 22 14 6 29 21 13 Reserved 5 VASYNW 28 20 12 4 27 Reserved 19 BLICNT 11 3 OCR1 26 18 10 2 25 17 9 OSDBLI 1 OCR0 24 16 8 OSDCKY 0 - 285 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:24] [23:16] [15:10] [9] Reserved BLICNT Reserved OSDBLI Reserved OSD Blinking Cycle Time An 8-bit value specifies the OSD blinking cycle time (unit: Vsync) Reserved OSD Blinking Control 0 = Disable 1 = Enable OSD Color Key Control 0 = Disable 1 = Enable Reserved Video Synthesis Weighting Synthesized video= [Video x VASYNW+ OSD x (8-VASYNW)]/8 Video/OSD overlay control 1 When display region with OSD window, color-key condition match 00 = Display video data 01 = Display OSD data 10 = Display synthesized (Video+OSD) data Video/OSD overlay control 0 When display region with OSD window, color-key condition un-match 00 = Display video data 01 = Display OSD data 10 = Display synthesized (Video+OSD) data [8] [7] [6:4] OSDCKY Reserved VASYNW [3:2] OCR1 [1:0] OCR0 OSD Overlay Color Key Pattern Register (OSDKYP) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDKYP 0xFFF0_80A8 R/W OSD Overlay Color-Key Pattern 0x0000_0000 - 286 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 OSDRKYP OSDGKYP OSDBKYP BITS DESCRIPTIONS [31:24] [23:16] [15:8] [7:0] Reserved OSDRKYP OSDGKYP OSDBKYP Reserved OSD data comparing of R component according to the source color format OSD data comparing of G component according to the source color format OSD data comparing of B component according to the source color format OSD Overlay Color Key Mask Register (OSDKYM) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDKYM 0xFFF0_80AC R/W OSD Overlay Color-Key Mask 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 OSDRKYM OSDGKYM OSDBKYM - 287 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:24] [23:16] [15:8] [7:0] Reserved OSDRKYM OSDGKYM OSDBKYM Reserved For color-key pattern mask of R component according to the source color format For color-key pattern mask of G component according to the source color format For color-key pattern mask of B component according to the source color format 7.10.3.7. LCD Timing Generation LCD Timing Controller Register 1 (LCDTCON1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDTCON1 0xFFF0_80B0 R/W LCD Timing Control Register 1 0x0000_0000 31 Reserved 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 HSPW_WLH 18 10 2 25 17 HBPD_WDLY 9 1 24 16 8 0 HSPW_WLH HBPD_WDLY HFPD_LINEBLANK BITS DESCRIPTIONS HFPD_LINEBLANK [31:30] Reserved HSPW WLH Reserved TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. STN: WLH bits determine the VLINE pulse's high level width by counting the number of the LCDCLK. TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. STN: WDLY bits determine the delay between VLINE and VCLK by Counting the number of the LCDCLK. [29:20] [19:10] HBPD WDLY - 288 - W90P710 Continued. BITS DESCRIPTIONS [9:0] HFPD LINEBLANK TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. STN: These bits indicate the blank time in horizontal line duration time. The unit of LINEBLANK is LCDCLK. LCD Timing Controller Register 2 (LCDTCON2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDTCON2 0xFFF0_80B4 R/W LCD Timing Control Register 2 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 PPL 20 PPL 12 LPP 4 LPP 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] PPL LPP Pixel Per-Line The PPL bit field specifies the number of pixels in each line or row of screen. Lines Per-Panel The LPP bit field specifies the number of active lines per screen. LCD Timing Controller Register 3 (LCDTCON3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDTCON3 0xFFF0_80B8 R/W LCD Timing Control Register 3 0x0000_0000 - 289 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 Reserved 23 15 7 30 22 VSPW 14 6 29 21 13 VBPD 5 28 20 12 4 VFPD 27 VSPW 19 11 3 26 18 VBPD 10 2 25 17 9 VFPD 1 24 16 8 0 BITS DESCRIPTIONS [31:30] [29:20] Reserved VSPW Reserved TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. STN: These bits should be set to zero on STN LCD. TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. STN: These bits should be set to zero on STN LCD. [19:10] VBPD [9:0] VFPD LCD Timing Controller Register 4 (LCDTCON4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDTCON4 0xFFF0_80BC R/W LCD Timing Control Register 4 0x0000_0000 31 23 15 7 30 22 14 6 29 Reserved 21 13 5 28 20 PCD 12 Reserved 4 LCDPRESC 27 19 11 3 26 18 10 2 25 PCD 17 9 1 24 16 BCD 8 PLLRDY 0 CLKSEL - 290 - W90P710 BITS DESCRIPTIONS [31:27] [26:17] [16] [15:9] [8] [7:1] [0] Reserved PCD BCD Reserved PLLRDY LCDPRESC CLKSEL Reserved The ten-bit PCD field is used to derive the LCD panel clock frequency VCLK from LCD controller clock: VCLK=(LCD controller clock)/(PCD+2) Bypass pixel clock divider. Reserved Indicate LCDC that PLL is ready, can switch pixel clock source to PLL clock These bits pre-scale counter the LCD controller clock Scale_CLK = PLL_FIN / ( 2*( LCDPRESC + 1 ) ) This bit driver the LCD controller clock source. 0 = external PLL clock 1 = AHB Bus clock LCD Timing Controller Register 5 (LCDTCON5) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDTCON5 0xFFF0_80C0 R/W LCD Timing Control Register 5 0x0000_0000 31 23 15 7 30 22 Reserved 14 6 Reserved 29 21 13 5 28 20 12 4 MMODE 27 Reserved 19 11 Reserved 3 INVVCLK 26 18 ACBF 10 2 INVHSYN 25 17 9 1 INVVSYN 24 16 8 0 INVVDEN - 291 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:21] [20:16] [15:5] [4] Reserved ACBF Reserved MMODE Reserved Determine the toggle rate of the VM (AC bias pin).The AC bias pin frequency is only applicable to STN display. Program this field with the number of line clocks between each toggle. Reserved Determine the toggle rate of the VM 0 = Each Frame 1 = The rate defined by the ACBF. STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = Normal 1 = Inverted TFT: This bit indicates the VDEN signal polarity. 0 = Normal 1 = Inverted [3] INVVCLK [2] INVHSYN [1] INVVSYN [0] INVVDEN LCD Timing Controller Register 6 (LCDTCON6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE LCDTCON6 0xFFF0_80C4 R LCD Timing Control Register 6 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 PPLCURENT PPLCURENT LPPCURENT LPPCURENT - 292 - W90P710 BITS DESCRIPTIONS [31:16] [15:0] PPLCURENT LPPCURENT Pixel number which LCD Controller is outputting to LCD Panel Line number which LCD Controller is outputting to LCD Panel Fig. 7.10.3.7.1 TFT Horizontal display timing diagram Fig. 7.10.3.7.2 TFT Vertical display timing diagram - 293 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Fig. 7.10.3.7.3 STN Horizontal display timing diagram Fig. 7.10.3.7.4 STN Vertical display timing diagram - 294 - W90P710 7.10.3.8. Palette SRAM Build In Self-Test Palette SRAM Build In Self Test Register (BIST) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE BIST 0xFFF0_80D0 R/W Palette SRAM Build In Self Test Register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 20 12 4 27 Reserved 19 Reserved 11 Reserved 3 26 18 10 2 FAIL 25 17 9 1 FINISH 24 16 8 0 BISTEN BITS DESCRIPTIONS [31:3] Reserved Reserved BIST Fail indicator 0 = SRAM BIST not fail 1 = SRAM BIST fail BIST Finish Status (Read Only) [2] FAIL [1] FINISH 0 = When BIST enabled, this value means BIST not finished 1 = When BIST enabled, this value means BIST finished, and FAIL can be referenced BIST Mode Enable [0] BISTEN 0 = SRAM is in normal operation. 1 = BIST enabled, SRAM is under BIST test - 295 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.11 Audio Controller The audio controller consists of IIS/AC-link protocol to interface with external audio CODEC. One 8-level deep FIFO for read path and write path and each level has 32-bit width (16 bits for right channel and 16 bits for left channel). One DMA controller handles the data movement between FIFO and memory. The following are the property of the DMA. * * * Always 8-beat incrementing burst Always bus lock when 8-beat incrementing burst When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically An AHB master port and an AHB slave port are offered in audio controller. 7.11.1 IIS Interface The IIS interface signals are shown as figure 7.11.2.1 MCLK BCLK Audio Controller LRCLK DOUT DIN Audio Codec Figure 7.11.2.1 The interface signal of IIS The 16 bits IIS and MSB-justified format are support, the timing diagram is shown as Figure 7.11.2.2 - 296 - W90P710 LRC LK L e ft R ig h t 1 BCK 2 3 1 2 DATA M SB B2 LSB M SB I2S b u s LRC LK L e ft R ig h t 1 BCK 2 3 1 2 DATA M SB B2 B3 LSB M SB B2 M S B - J u s tif ie d f o r m a t Figure 7.11.2.2 The format of IIS The sampling rate, bit shift clock frequency could be set by the control register ACTL_IISCON. 7.11.2 AC97 Interface The AC97 interface, called AC-link is supported. For input and output direction, each frame contains a Tag slot and 12 data slots. However, in the 12 data slots, only 4 slots are used in W90P710, other 8 slots are not supported, and the control data and audio data are transferred in the 4 valid slots. Each slot contains 20 bits data. The interface signals are shown as Figure 7.11.2.1 SYNC BCLK Audio Controller DIN DOUT RESETB Audio Codec Figure 7.11.2.1 The interface signal of AC-link The signal format is shown as Figure 7.11.2.2 Publication Release Date: January 17, 2005 Revision A.2 - 297 - W90P710 Frame (48 KHz) SYN BCL DIN DOU 12.288 MHz Tag phase Data phase . . . B255 B0 B1 B15 B16 . . . B35 B36 . . . B55 B56 . . . B75 B76 . . . B95 B96 . . . B255 MS Slot 0 LS Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 -12 Figure 7.11.2.2 The signal format of AC-link The structure of output frame is shown as below: SLOT # CONTENT BITS PHASE 0 Tag 15-0 Tag phase 1 CMD 2 CMD 3 PCM 4 PCM 5 6 7 8 9 10 11 12 ADDR DATA 19-0 19-0 LEFT RIGHT 19-0 19-0 Data phase Unused 159 - 0 The output frame data format is shown as following: SLOT # BIT DESCRIPTION 15 Tag (slot 0) 14 - 3 2-0 Frame validity bit, 1 is valid, 0 is invalid. Slot validity, but in W90P710, only bits 6-3 are used, bits 14-7 are unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot 2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared to 0. This field should be cleared to 0. - 298 - W90P710 Continued. SLOT # BIT DESCRIPTION CMD ADDR (slot 1) CMD DATA (slot 2) PCM LEFT (slot 3) PCM RIGHT (slot 4) 19 18-12 11 - 0 19 - 4 3-0 19 - 4 3-0 19 - 4 3-0 Read/write control, 1 for read and 0 for write Control register address This field should be cleared to 0 Control register write data. It should be cleared to 0 if current operation is read. This field should be cleared to 0 PCM playback data for left channel This field should be cleared to 0 PCM playback data for right channel This field should be cleared to 0 The structure of input frame is shown as below: Slot # Content Bits 0 Tag 0-15 1 status ADDR 19-0 2 status DATA 19-0 3 PCM LEFT 19-0 4 PCM RIGHT 19-0 Unused 159 - 0 5 6 7 8 9 10 11 12 The input frame data format is shown as following: SLOT # BIT DESCRIPTION 15 Tag (slot 0) 14 - 3 2-0 19 18-12 Status ADDR (slot 1) 11 10 9-0 Status DATA (slot 2) 19 - 4 3-0 Frame validity bit, 1 is valid, 0 is invalid. Slot validity, but in W90P710, only bits 6-3 are used, bits 14-7 are unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot 2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared to 0. This field should be cleared to 0. This bit should be cleared to 0 Control register address echo which previous frame requested PCM data for left channel request, it should be always 0 when VRA=0 (VRA: Variable Rate Audio mode). PCM data for right channel request (Same as Bit 11). This field should be cleared to 0 Control register read data which previous frame requested. It should be cleared to 0 if this slot is invalid. This field should be cleared to 0 - 299 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued SLOT # BIT DESCRIPTION PCM LEFT (slot 3) PCM RIGHT (slot 4) 19 - 4 3 -0 19 - 4 3 -0 PCM record data for left channel This field should be cleared to 0 PCM record data for right channel This field should be cleared to 0 - 300 - W90P710 7.11.3 Audio Controller Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_CON ACTL_RESET ACTL_RDSTB 0xFFF0_9000 R/W Audio controller control register 0xFFF0_9004 R/W Sub block reset control register 0xFFF0_9008 R/W 0x0000_0000 0x0000_0000 DMA destination base address register 0x0000_0000 for record DMA destination length register for ACTL_RDST_LENGT 0x0000_0000 0xFFF0_900C R/W record H ACTL_RDSTC ACTL_RSR ACTL_PDSTB 0xFFF0_9010 R DMA destination register for record current address 0x0000_0000 0x0000_0000 0xFFF0_9014 R/W 0xFFF0_9018 R/W Record status register DMA destination base address register 0x0000_0000 for play DMA destination length register for 0x0000_0000 play DMA destination register for play Play status register current address 0x0000_0000 0x0000_0004 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0080 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 ACTL_PDST_LENGTH 0xFFF0_901C R/W ACTL_PDSTC ACTL_PSR ACTL_IISCON ACTL_ACCON ACTL_ACOS0 ACTL_ACOS1 ACTL_ACOS2 ACTL_ACIS0 ACTL_ACIS1 ACTL_ACIS2 0xFFF0_9020 R 0xFFF0_9024 R/W 0xFFF0_9028 R/W IIS control register 0xFFF0_902C R/W AC-link control register 0xFFF0_9030 R/W AC-link out slot 0 0xFFF0_9034 R/W AC-link out slot 1 0xFFF0_9038 R/W AC-link out slot 2 0xFFF0_903C 0xFFF0_9040 0xFFF0_9044 R R R AC-link in slot 0 AC-link in slot 1 AC-link in slot 2 Audio controller control registers (ACTL_CON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_CON 0xFFF0_9000 R/W Audio controller control register 0x0000_0000 The ACTL_CON register control the basic operation of audio controller. - 301 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 Reserved 30 22 14 Reserved 29 21 13 Reserved 28 20 12 27 19 11 26 18 10 25 17 9 24 16 8 IIS_AC_PIN_S EL R_DMA_IRQ T_DMA_IRQ Reserved 2 1 7 FIFO_TH 6 Reserved 5 4 Reserved 3 0 Reserved BLOCK_EN[1:0] BITS DESCRIPTIONS Reserved Reserved Reserved When recording, when the DMA destination current address reach the DMA destination end address or middle address, the R_DMA_IRQ bit will be set to 1 automatically, and this bit could be cleared to 0 by CPU. The bit is hardwired to ARM as interrupt request signal with an inverter. The R_DMA_IRQ bit is read/write (write 1 to clear) Transmit DMA interrupt request bit. When DMA current address reach the middle address (((ACTL_DESE - ACTL_DESB)-1)/2 + ACTL_DESB) or reach the end address ACTL_DESB, the bit T_DMA_IRQ will be set to 1, and this bit could be clear to 0 by write "1" by CPU. And the bit is hardwired to ARM as interrupt request signal with an inverter. The T_DMA_IRQ bit is read/write (write 1 to clear). IIS or AC-link pin selection [15] [14] [13] [12] R_DMA_IRQ [11] T_DMA_IRQ [8] IIS_AC_PIN_SEL * If IIS_AC_PIN_SEL = 0, the pins select IIS * If IIS_AC_PIN_SEL = 1, the pins select AC-link The IIS_AC_PIN_SEL bis is read/write FIFO threshold control bit [7] FIFO_TH * If FIFO_TH=0, the FIFO threshold is 8 level * If FIFO_TH=1, the FIFO threshold is 4 level The FIFO_TH bit is read/write [6] Reserved - 302 - W90P710 Continued. BITS DESCRIPTIONS Audio interface type selection * If BLOCK_EN[0]=0/1, IIS interface is disable/enable * If BLOCK_EN[1]=0/1, AC-link interface is disable/enable The BLOCK_EN[1:0] bits are read/write [2:1] [0] BLOCK_EN[1:0] Reserved Sub-block reset control register (ACTL_RESET) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_RESET 0xFFF0_9004 R/W Sub block reset control 0x0000_0000 The value in ACTL_RESET register control the reset operation in each sub block. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ACTL_RESET 15 14 13 12 11 10 Reserved 9 8 AC_RECOR D RECORD_SINGLE[1:0] 7 AC_PLAY 6 IIS_RECORD PLAY_SINGLE[1:0] 5 IIS_PLAY 4 3 Reserved 2 1 AC_RESET 0 IIS_RESET BITS DESCRIPTIONS [31:17] Reserved Audio controller reset control bit 1 = the whole audio controller is reset 0 = the audio controller is normal operation The ACTL_RESET bit is read/write record single/dual channel select bits 2'b11= the record is dual channel 2'b01= the record only select left channel 2'b10= the record only select right channel 2'b00 is reserved Note that, when ADC is selected as record path, it only support left channel record. The PLAY_SINGLE[1:0] bits are read/write Publication Release Date: January 17, 2005 Revision A.2 [16] ACTL_RESET [15:14] RECORD_SINGLE [1:0] - 303 - W90P710 Continued. BITS DESCRIPTIONS [13:12] PLAY_SINGLE [1:0] Playback single/dual channel select bits PLAY_SINGLE[1:0]=11, the playback is in stereo mode PLAY_SINGLE[1:0]=10, the playback is in mono mode PLAY_SINGLE[1:0]= 00 & 01 is reserved The PLAY_SINGLE[1:0] bits are read/write AC link record control bit AC_RECORD=0, the record path of AC link is disable AC_RECORD=1, the record path of AC link is enable The AC_RECORD bit is read/write AC link playback control bit AC_PLAY=0, the playback path of AC link is disable AC_PLAY=1, the playback path of AC link is enable The AC_PLAY bit is read/write IIS record control bit IIS_RECORD=0, the record path of IIS is disable IIS_RECORD=1, the record path of IIS is enable The IIS_RECORD bit is read/write IIS playback control bit IIS_PLAY=0, the playback path of IIS is disable IIS_PLAY=1, the playback path of IIS is enable The IIS_PLAY bit is read/write AC link sub block RESET control bit AC_RESET=0, release the AC link function block from reset mode AC_RESET=1, force the AC link function block to reset mode The AC_RESET bit is read/write IIS sub block RESET control bit IIS_RESET=0, release the IIS function block from reset mode IIS_RESET=1, force the IIS function block to reset mode The IIS_RESET bit is read/write [8] AC_RECORD [7] AC_PLAY [6] IIS_RECORD [5] IIS_PLAY [1] AC_RESET [0] IIS_RESET DMA record destination base address (ACTL_RDSTB) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_RDSTB 0xFFF0_9008 R/W DMA record destination base address 0x0000_0000 The value in ACTL_RDSTB register is the record destination base address of DMA, and only could be changed by CPU. - 304 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 AUDIO_RDSTB[31:24] AUDIO_RDSTB[23:16] AUDIO_RDSTB[15:8] AUDIO_RDSTB[7:0] BITS DESCRIPTIONS [31:0] AUDIO_RDSTB[31:0] 32-bit record destination base address The AUDIO_RDSTB[31:0] bits is read/write. DMA destination end address (ACTL_RDST_LENGTH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_RDST_LENGTH 0xFFF0_900 DMA record R/W C length destination address 0x0000_0000 The value in ACTL_RDST_LENGTH register is the record destination address length of DMA, and the register could only be changed by CPU. 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 AUDIO_RDST_L[31:24] AUDIO_RDST_L[23:16] AUDIO_RDST_L[15:8] AUDIO_RDST_L[7:0] - 305 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS [31:0] AUDIO_RDST_L[31:0] DESCRIPTIONS 32-bit record destination address length The AUDIO_RDST_L[31:0] bits is read/write. DMA destination current address (ACTL_RDSTC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_RDSTC 0xFFF0_9010 RO DMA record destination current address 0x0000_0000 The value in ACTL_RDSTC is the DMA record destination current address, this register could only be read by CPU. 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 AUDIO_RDSTC[31:24] AUDIO_RDSTC[23:16] AUDIO_RDSTC[15:8] AUDIO_RDSTC[7:0] BITS DESCRIPTIONS [31:0] AUDIO_RDSTC[31:0] 32-bit record destination current address The AUDIO_RDSTC[31:0] bits is read only. Audio controller record status register (ACTL_RSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_RSR 0xFFF0_9014 R/W Audio controller FIFO and DMA status register for record 0x0000_0000 - 306 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 20 12 4 27 19 11 3 26 Reserved 18 Reserved 10 Reserved 2 R_FIFO_FULL 25 17 9 1 24 16 8 0 R_DMA_END_IRQ R_DMA_MIDDLE_IRQ BITS DESCRIPTIONS [31:3] Reserved Record FIFO full indicator bit R_FIFO_FULL=0, the record FIFO not full R_FIFO_FULL=1, the record FIFO is full The R_FIFO_READY bit is read only DMA end address interrupt request bit for record R_DMA_END_IRQ=0, means record DMA address does not reach the end address R_DMA_END_IRQ=1, means record DMA address reach the end address The R_DMA_END_IRQ bit is readable, and only can be clear by write "1" to this bit DMA address interrupt request bit for record [2] R_FIFO_FULL [1] R_DMA_END_IRQ [0] R_DMA_MIDDLE _IRQ R_DMA_MIDDLE_IRQ=0, means record DMA address does not reach the middle address R_DMA_MIDDLE_IRQ=1, means record DMA address reach the middle address The R_DMA_MIDDLE_IRQ bit is readable, and only can be clear by write "1" to this bit DMA play destination base address (ACTL_PDSTB) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_PDSTB 0xFFF0_9018 R/W DMA play destination base address 0x0000_0000 - 307 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 The value in ACTL_PDSTB register is the play destination base address of DMA, and only could be changed by CPU. 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 AUDIO_PDSTB[31:24] AUDIO_PDSTB[23:16] AUDIO_PDSTB[15:8] AUDIO_PDSTB[7:0] BITS DESCRIPTIONS [31:0] AUDIO_PDSTB[31:0] 32-bit play destination base address The AUDIO_PDSTB[31:0] bits is read/write. DMA destination end address (ACTL_PDST_LENGTH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_PDST_LENGTH 0xFFF0_901 R/W DMA play destination address length C 0x0000_0000 The value in ACTL_PDST_LENGTH register is the play destination address length of DMA, and the register could only be changed by CPU. 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 AUDIO_PDST_L[31:24] AUDIO_PDST_L[23:16] AUDIO_PDST_L[15:8] AUDIO_PDST_L[7:0] - 308 - W90P710 BITS DESCRIPTIONS [31:0] AUDIO_PDST_L[31:0] 32-bit play destination address length The AUDIO_PDST_L[31:0] bits is read/write. DMA destination current address (ACTL_PDSTC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_PDSTC 0xFFF0_9020 RO DMA play destination current address 0x0000_0000 The value in ACTL_PDSTC is the DMA play destination current address, this register could only be read by CPU. 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 AUDIO_PDSTC[31:24] AUDIO_PDSTC[23:16] AUDIO_PDSTC[15:8] AUDIO_PDSTC[7:0] BITS DESCRIPTIONS [31:0] AUDIO_PDSTC[31:0] 32-bit play destination current address The AUDIO_PDSTC[31:0] bits is read/write. Audio controller playback status register (ACTL_PSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_PSR 0xFFF0_9024 R/W Audio controller FIFO and DMA status register for playback 0x0000_0004 - 309 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 20 12 4 27 19 11 3 26 Reserved 18 Reserved 10 Reserved 2 P_FIFO_EMPTY 25 17 9 1 P_DMA_END_IRQ 24 16 8 0 P_DMA_MIDDL E_IRQ BITS DESCRIPTIONS [31:3] Reserved Playback FIFO empty indicator bit [2] P_FIFO_EMPTY P_FIFO_EMPTY=0, the playback FIFO is not empty P_FIFO_EMPTY=1, the playback FIFO is empty The P_FIFO_EMPTY bit is read only DMA end address interrupt request bit for playback P_DMA_END_IRQ=0, means playback DMA address does not reach the end address P_DMA_END_IRQ=1, means playback DMA address reach the end address The P_DMA_END_IRQ bit is readable, and only can be clear by write "1" to this bit DMA address interrupt request bit for playback [1] P_DMA_END_IRQ [0] P_DMA_MIDDLE _IRQ P_DMA_MIDDLE_IRQ=0, means playback DMA address does not reach the middle address P_DMA_MIDDLE_IRQ=1, means playback DMA address reach the middle address The P_DMA_MIDDLE_IRQ bit is readable, and only can be clear by write "1" to this bit IIS control register (ACTL_IISCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_IISCON 0xFFF0_9028 R/W IIS control register 0x0000_0000 The ACTL_IISCON is the IIS basic operation control register. - 310 - W90P710 31 23 15 7 30 22 14 6 29 21 Reserved 13 5 FS_SEL 28 Reserved 20 12 Reserved 4 MCLK_SEL 27 19 11 3 FORMAT 26 18 10 2 25 17 PRS[3:0] 9 1 Reserved 24 16 8 0 BCLK_SEL[1:0] BITS DESCRIPTIONS [31:20] Reserved IIS frequency pre-scaler selection bits. (FPLL is the input PLL frequency, MCLK is the output main clock) PSR[3:0]=0000, MCLK=FPLL/1 PSR[3:0]=0001, MCLK=FPLL/2 PSR[3:0]=0010, MCLK=FPLL/3 PSR[3:0]=0011, MCLK=FPLL/4 PSR[3:0]=0100, MCLK=FPLL/5 PSR[3:0]=0101, MCLK=FPLL/6 PSR[3:0]=0110, MCLK=FPLL/7 PSR[3:0]=0111, MCLK=FPLL/8 [19:16] PRS[3:0] PSR[3:0]=1000, reserved PSR[3:0]=1001, MCLK=FPLL/10 PSR[3:0]=1010, reserved PSR[3:0]=1011, MCLK=FPLL/12 PSR[3:0]=1100, reserved PSR[3:0]=1101, MCLK=FPLL/14 PSR[3:0]=1110, reserved PSR[3:0]=1111, MCLK=FPLL/16 (when the division factor is 3/5/7, the duty cycle of MCLK is not 50%, the high duration is 0.5*FPLL) The PSR[3:0] bits are read/write - 311 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS IIS serial data clock frequency selection bit BCLK_SEL[1:0]=00, 32fs is selected (fs is sampling rate), when FS_SEL=0, the frequency of bit clock is MCLK/8, when FS_SEL=1, the frequency of bit clock is MCLK/12. BCLK_SEL[1:0]=01, 48fs is selected (only when FS_SEL=1, this term could be selection), when FS_SEL=1, the frequency of bit clock is MCLK/8. The BCLK_SEL[1:0] bits are read/write IIS sampling frequency selection bit [5] FS_SEL FS_SEL=0, FMCLK/256 is selected (FMCLK is the frequency of signal MCLK) FS_SEL=1, FMCLK/384 is selected The FS_SEL bit is read/write IIS MCLK output selection bit [4] MCLK_SEL MCLK_SEL=0, IIS MCLK output will follow the PRS[3:0] setting. MCLK_SEL=1, IIS MCLK output will be the same with FPLL. The MCLK_SEL bit is read/write IIS format selection bits [3] FORMAT FORMAT=0, IIS compatible format is selected FORMAT=1, MSB-justified format is selected The FORMAT bit is read/write - [7:6] BCLK_SEL [1:0] [2:0] Reserved AC-link Control Register (ACTL_ACCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACCON 0xFFF0_902 R/W C AC-link control register 0x0000_0000 The ACTL_ACCON register is the AC-link basic operation control register. - 312 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 AC_BCLK_ PU_EN 28 Reserved 20 Reserved 12 Reserved 4 AC_R_FINI SH 27 19 11 3 AC_W_FINI SH 26 18 10 2 AC_W_RE S 25 17 9 1 AC_C_RES 24 16 8 0 Reserved Reserved BITS DESCRIPTIONS [6] Reserved This bit controls the AC_BCLK pin pull-high resister. AC_BCLK_PU_EN=0, the AC_BCLK pin pull-high resister will be disabled AC_BCLK_PU_EN=1, the AC_BCLK pin pull-high resister will be enabled The AC_BCLK_PU_EN bit is read/write. AC-link read data ready bit. When read data indexed by previous frame is shifted into ACTL_ACIS2, the AC_R_FINISH bit will be set to 1 automatically. After CPU read out the read data, AC_R_FINISH bit will be cleared to 0. AC_R_FINISH=0, read data buffer has been read by CPU AC_R_FINISH=1, read data buffer is ready for CPU read The AC_R_FINISH bit is read only AC-link write frame finish bit. When writing data to register ACTL_ACOS0, the AC_W_FINISH bit will be set to 1 automatically. After AC-link interface shift out the register ACTL_ACOS0, the AC_W_FINISH bit will be cleared to 0. AC_W_FINISH=0, AC-link control data out buffer has been shifted out to codec by CPU and data out buffer is empty. AC_W_FINISH=1, AC-link control data out buffer is ready to be shifted out(After users have wrote data into register ACTL_ACOS0) The AC_W_FINISH bit is read only [5] AC_BCLK_PU_EN [4] AC_R_FINISH [3] AC_W_FINISH - 313 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS [2] AC_W_RES AC-link warm reset control bit, when this bit is set to 1, (AC-link begin warn reset procedure, after warn reset procedure finished, this bit will be cleared automatically) the interface signal AC_SYNC is high, when this bit is set to 0, the interface signal AC_SYNC is controlled by AC_BCLK input when this bit is set to 1. Note the AC-link spec. shows it need at least 10 us high duration of AC_SYNC to warn reset AC97. AC_W_RES=0, AC_SYNC pin is controlled by AC_BCLK input pin AC_W_RES=1, AC_SYNC pin is forced to high The AC_W_RES bit is read/write AC-link cold reset control bit, when this bit is set to 1, the interface signal AC_RESETB is low, when this bit is set to 0, the signal AC_RESETB is high. Note the AC-link spec. shows it need at least 10 us low duration of AC_RESETB to cold reset AC97. AC_C_RES=0, AC_RESETB pin is set to 1 AC_C_RES=1, AC_RESETB pin is set to 0 The AC_C_RES bit is read/write - [1] AC_C_RES [0] Reserved AC-link output slot 0 (ACTL_ACOS0) REGISTER ADDRESS R/W DESCRIPTION AC-link out slot 0 RESET VALUE ACTL_ACOS0 0xFFF0_9030 R/W 0x0000_0000 The ACTL_ACOS0 register store the slot 0 value to be shift out by AC-link. Note that write data to ACTL_ACOS0 register when AC_W_FINISH bit (ACTL_ACCON[3]) is set is invalid. Therefore, check AC_W_FINISH bit status before write data into ACTL_ACOS0 register. 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 VALID_ FRAME 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 SLOT_VALID[3:0] - 314 - W90P710 BITS DESCRIPTIONS [31:5] Reserved Frame valid indicated bits VALID_FRAME=1, any one of slot is valid VALID_FRAME=0, no any slot is valid The VALID_FRAME bits are read/write Slot valid indicated bits SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid The SLOT_VALID[3:0] bits are read/write [4] VALID_FRAME [3:0] SLOT_VALID [3:0] The AC-link output slot 1 (ACTL_ACOS1) REGISTER ADDRESS R/W DESCRIPTION AC-link out slot 1 RESET VALUE ACTL_ACOS1 0xFFF0_9034 R/W 0x0000_0080 The ACTL_ACOS1 register store the slot 1 value to be shift out by AC-link. 31 23 15 7 R_WB 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 3 R_INDEX[6:0] 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 - 315 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:8] Reserved Read/Write select bit R_WB=1, a read specified by R_INDEX[6:0] will occur, and the data will appear in next frame R_WB=0, a write specified by R_INDEX[6:0] will occur, and the write data is put at out slot 2 The R_WB bit is read/write External AC97 CODEC control register index (address) bits The R_INDEX[6:0] bits are read/write [7] R_WB [6:0] R_INDEX[6:0] AC-link output slot 2 (ACTL_ACOS2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACOS2 0xFFF0_9038 R/W AC-link out slot 2 0x0000_0000 The ACTL_ACOS2 register store the slot 2 value to be shift out by AC-link. 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 WD[15:8] 4 WD[7:0] 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 BITS DESCRIPTIONS [31:0] [15:0] Reserved WD[15:0] AC-link write data The WD[15:0] bits are read/write - 316 - W90P710 AC-link input slot 0 (ACTL_ACIS0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACIS0 0xFFF0_903 C R AC-link in slot 0 0x0000_0000 The ACTL_ACIS0 store the shift in slot 0 data of AC-link. 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 CODEC_READ Y 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 SLOT_VALID[3:0] BITS DESCRIPTIONS [31:5] Reserved External AC97 audio CODEC ready bit [4] CODEC_READY CODEC_READY=0, indicate external AC97 audio CODEC is not ready CODEC_READY=1, indicate external AC97 audio CODEC is ready The CODEC_READY bit is read only Slot valid indicated bits [3:0] SLOT_VALID[3:0] SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid The SLOT_VALID[3:0] bits are read AC-link input slot 1 (ACTL_ACIS1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACIS1 0xFFF0_9040 R AC-link in slot 1 0x0000_0000 - 317 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 The ACTL_ACIS1 stores the shift in slot 1 data of AC-link. 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 Reserved 4 3 2 1 R_INDEX[5:0] 27 Reserved 19 Reserved 11 10 9 8 R_INDEX[6] 26 18 25 17 24 16 0 SLOT_REQ[1:0] BITS DESCRIPTIONS [31:9] [8:2] Reserved R_INDEX[6:0] Register index. The R_INDEX[6:0] echo the register index (address) when a register read has been requested in the previous frame. The R_INDEX[6:0] bits are read only Slot request. The bits indicate if the external codec need new PCM data that will transfer in next frame. [1:0] SLOT_REQ[1:0] Any bit in SLOT_REQ[1:0] is set to 1, indicate external codec does not need a new sample in the corresponding slot[3:4] of the next frame Any SLOT_REQ[1:0] is clear to 0, indicate external codec need a new sample in the corresponding slot[3:4] of the next frame The SLOT_REQ[1:0] bits are read only AC-link input slot 2 (ACTL_ACIS2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACIS2 0xFFF0_9044 R AC-link in slot 2 0x0000_0000 The ACTL_ACIS2 stores the shift in slot 2 data of AC-link. - 318 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 RD[15:8] 4 RD[7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:16] [15:0] Reserved RD[15:0] AC-link read data. The RD[15:0] bits are read only - 319 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.12 Universal Asynchronous Receiver/Transmitter Controller Asynchronous serial communication block include 4 UART blocks and accessory logic. They can be described as follow: * UART0 It is merely a general purpose UART. It does not include any accessory function. Clock Source UART Type FIFO Number Modem Function Accessory Function * UART1 It is designed for general purpose UART or Bluetooth transceiver. It includes a high speed UART block with 64-byte receiving FIFO and 64-byte transmitting FIFO. It includes 3 clock sources: 15M, 30M, and 43.6M. Programmer can feel free to choose the clock source and divisor number for suitable baud rate. Clock Source : 15MHz from external crystal 30M, 43.6M, 48M, 60M (optional function for Bluetooth HCI transport layer) UAR Type FIFO Number Modem Function Accessory Function Baud Rate (max) I/O pin * UART2 It is designed for general purpose UART or IrDA SIR. The part of UART includes 16-byte receiving FIFO and 16-byte transmitting FIFO. The UART is same as the UART of W90N740 but without modem function. The U3 block has merely 2 I/O. TXD2/RXD2 of UART2 occupy the same pins with RTS and CTS of UART1. Once the Bluetooth function has been enabled, UART2 should be disabled. Clock Source UART Type FIFO Number Modem Function : 15MHz : general UART, it is same as the UART of W90N740 : 16-byte receiving FIFO and 16 byte transmitting FIFO : N/A - 320 : high speed UART, it is same as the UART of W99702 : 64-byte receiving FIFO and 64 byte transmitting FIFO : CTS and RTS (optional for Bluetooth. If they were enabled, TX & RX in UART2 will be cut off) : Bluetooth (optional) : 1.875MHz : TXD1, RXD1, RTS, CTS (optional) : 15MHz : general UART, it is same as the UART of W90N740 : 16-byte receiving FIFO and 16 byte transmitting FIFO : N/A : N/A W90P710 Accessory Function : IrDA SIR (optional) I/O Pin I/O Pin Share with * UART3 It is also merely a general purpose UART. It does not include any accessory function. It share four I/O pins with AC97/I2S. Clock Source UART Type FIFO Number Modem Function Accessory Function I/O Pin I/O Pin Share with : 15MHz : general UART, it is same as the UART of W90N740 : 16-byte receiving FIFO and 16 byte transmitting FIFO : DTR, DSR : N/A : TXD3, RXD3, DTR, DSR : AC97_DATAO, AC97_DATAI, AC97_SYNC, AC97_BITCLK Table 7.12.1 W90P710 UART features list BLOCK NUMBER UART TYPE General UART High speed UART General UART General UART : TXD2, RXD2. : UART1 (Bluetooth function) CLOCK SOURCE 15M 15M, 43.6M, 60M 15M 30M, 48M, MODEM FUNCTION SIGNALS N/A IO PINS TxD0, RXD0 TXD1, RXD1, CTS1, RTS1 TX2, RX2 TXD3, RXD3, DRT3, DSR3 DESIGN TARGET General UART General Bluetooth General SIR UART/ 0 1 CTS, RTS 2 N/A UART/IrDA 3 15M DTR, DSR General UART - 321 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.12.1 UART0 UART0 is a general UART block. It is same as the UART in W90N740 but without Modem I/O signals. More detail function description, please refer to section 7.12.5 General UARTcontroller description Table 7.12.1.1 UART0 Register Map REGISTER ADDRESS R/W OTHER CONDITION RESET VALUE UART0_RBR UART0_THR UART0_IER UART0_DLL UART0_DLM UART0_IIR UART0_FCR UART0_LCR Reserved UART0_LSR Reserved UART0_TOR 0xFFF8_0000 0xFFF8_0000 0xFFF8_0004 0xFFF8_0000 0xFFF8_0004 0xFFF8_0008 0xFFF8_0008 0xFFF8_000c 0xFFF8_0010 0xFFF8_0014 0xFFF8_0018 0xFFF8_001c R W R/W R/W R/W R W R/W DLAB=0 DLAB=0 DLAB=0 DLAB=1 DLAB=1 Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 R 0x6060_6060 R/W 0x0000_0000 7.12.2 UART1 The UART1 is designed for general purpose UART or Bluetooth HCI transport layer. It is a high speed UART with 64-byte receive FIFO and 64-byte transmit FIFO. To perform 1.875MHz maximum baud rate, UART1 has 5 clock sources, 15M, 30M, 43.6M, 48M, and 60M. The first one is from external 15M crystal clock and the other are divided from system PLL 480MHz output. More detail about high speed UART, please refer to next section 7.12.6 High Speed UART controller function description. The block UART1 offer 4 I/O signals, TX, RX, CTS, and RTS. CTS and RTS are used as flow control for Bluetooth. CTS and RTS share the same I/O pins with TX and RX in block UART2. - 322 - W90P710 Table 7.12.2.1 UART1 Register Map REGISTER ADDRESS 0xFFF8_0100 0xFFF8_0100 0xFFF8_0104 0xFFF8_0100 0xFFF8_0104 0xFFF8_0108 0xFFF8_0108 0xFFF8_010c 0xFFF8_0110 0xFFF8_0114 0xFFF8_0118 0xFFF8_011c 0xFFF8_0120 R/W R W R/W R/W R/W R W R/W R/W R R R/W R/W OTHER CONDITION DLAB=0 DLAB=0 DLAB=0 DLAB=1 DLAB=1 RESET VALUE Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 0x0000_0000 UART1_RBR UART1_THR UART1_IER UART1_DLL UART1_DLM UART1_IIR UART1_FCR UART1_LCR UART1_MCR UART1_LSR UART1_MSR UART1_TOR UART1_UBCR UART1 Bluetooth Control Register (UART1_UBCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART1_UBCR 0xFFF8_0120 31 23 15 7 30 22 14 6 29 21 13 5 R/W UART 1 Bluetooth Control Register 28 Reserved 20 Reserved 12 Reserved 4 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 Reserved UBCR[2:0] - 323 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:3] Reserved UBCR is a 3 bits register which is used to select clock source to generate suitable baud rate: 000: 15Mhz from external crystal [2:0] UBCR 100: 30Mhz divided from PLL 480Mhz 101: 43.6Mhz divided from PLL 480Mhz 110: 48Mhz divided from PLL 480Mhz 111: 60Mhz divided from PLL 480Mhz 7.12.3 UART2 UART2 contains 2 features: general UART and IrDA SIR decoder/encoder. UART is same as the UART of W90N740 but without modem function. Please read the spec of section 7.12.5 General UART controller function description. The IrDA SIR is described as follow: Table 7.12.3.1 UART2 Register Map Register UART2_RBR UART2_THR UART2_IER UART2_DLL UART2_DLM UART2_IIR UART2_FCR UART2_LCR Reserved UART2_LSR Reserved UART2_TOR UART2_IRCR Address 0xFFF8_0200 0xFFF8_0200 0xFFF8_0204 0xFFF8_0200 0xFFF8_0204 0xFFF8_0208 0xFFF8_0208 0xFFF8_020c 0xFFF8_0210 0xFFF8_0214 0xFFF8_0218 0xFFF8_021c 0xFFF8_0220 R/W R/W R R/W R W R/W R/W R/W R W R/W Other condition DLAB=0 DLAB=0 DLAB=0 DLAB=1 DLAB=1 Reset value Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 Undefined 0x6060_6060 Undefined 0x0000_0000 0x0000_0040 UART2 IrDA Control Register (UART2_IRCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART2_IRC R 0xFFF8_0220 R/W UART 2 IrDA Control Register 0x0000_0040 - 324 - W90P710 31 23 15 7 Reserved 30 22 14 6 INV_RX 29 21 13 5 INV_TX 28 Reserved 20 Reserved 12 Reserved 4 Reserved 3 Reserved 2 LB 1 0 11 10 9 8 19 18 17 16 27 26 25 24 TX_SELECT IrDA_EN BITS DESCRIPTIONS [31:7] [6] Reserved INV_RX Reserved 1: Inverse RX input signal 0: No inversion 1: Inverse TX output signal 0: No inversion Reserved IrDA loop back mode for self test. [5] [4:3] INV_TX Reserved [2] LB 1: enable IrDA loop back mode 0: disable IrDA loop back mode [1] TX_SELECT 1: enable IrDA transmitter 0: enable IrDA receiver 1: enable IrDA block 0: disable IrDA block [0] IrDA_EN - 325 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.12.4 UART3 UART3 is a general UART block. It is same as the UART in W90N740 but with some Modem I/O signals. More detail general UART function description, please refer to next section 7.12.5 General UART controller. Table 7.12.4.1 UART3 register map REGISTER UART3_RBR UART3_THR UART3_IER UART3_DLL UART3_DLM UART3_IIR UART3_FCR UART3_LCR UART3_MCR UART3_LSR UART3_MSR UART3_TOR ADDRESS 0xFFF8_0300 0xFFF8_0300 0xFFF8_0304 0xFFF8_0300 0xFFF8_0304 0xFFF8_0308 0xFFF8_0308 0xFFF8_030c 0xFFF8_0310 0xFFF8_0314 0xFFF8_0318 0xFFF8_031c R/W R W R/W R/W R/W R W R/W R/W R R R/W OTHER CONDITION DLAB=0 DLAB=0 DLAB=0 DLAB=1 DLAB=1 RESET VALUE Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 UART3 Modem Control Register (UART3_MCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART3_MCR 0xFFF8_0310 31 23 15 7 Reserved 30 22 14 6 Reserved 29 21 13 5 R/W UART 3 Modem Control Register 0x0000_0000 28 Reserved 20 Reserved 12 Reserved 4 LBME 27 19 11 3 Reserved 26 18 10 2 Reserved 25 17 9 1 Reserved 24 16 8 0 DTR# Reserved Note: UART3_MCR is subset of MCR in W90N740. Please refer to section 7.13.5 `General UART'. - 326 - W90P710 UART3 Modem Status Register (UART3_MSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART3_MSR 0xFFF8_0318 31 23 15 7 Reserved 30 22 14 6 Reserved 29 21 13 5 R UART 3 Modem Status Register 0x0000_0000 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 Reserved 26 18 10 2 Reserved 25 17 9 1 DDSR 24 16 8 0 Reserved DSR# Note: MSR is subset of MSR in W90N740. Please refer to section 7.13.5 `General UART'. 7.12.5 General UART Controller The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data characters received from the peripheral such as MODEM, and a parallel-to-serial conversion on data characters received from the CPU. There are five types of interrupts, i.e., line status interrupt, transmitter FIFO empty interrupt, receiver threshold level reaching interrupt, time out interrupt, and MODEM status interrupt. One 16-byte transmitter FIFO (TX_FIFO) and one 16-byte (plus 3-bit of error data per byte) receiver FIFO (RX_FIFO) has been built in to reduce the number of interrupts presented to the CPU. The CPU can completely read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt) found. The UART includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver needed. The equation is BaudOut = crystal clock / 16 * [Divisor + 2]. The UART includes the following features: Transmitter and receiver are buffered with a 16-byte FIFO each to reduce the number of interrupts presented to the CPU. Subset of MODEM control functions (DSR, DTR, by IP selection) Fully programmable serial-interface characteristics: ---5-, 6-, 7-, or 8-bit character Even, odd, or no-parity bit generation and detection 1-, 1&1/2, or 2-stop bit generation Publication Release Date: January 17, 2005 Revision A.2 - 327 - W90P710 -Baud rate generation Line break generation and detection False start bit detection Full prioritized interrupt system controls Loop back mode for internal diagnostic testing 7.12.5.1. REGISTER UART Control Registers Map OFFSET R/W DESCRIPTION RESET VALUE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written R W R/W R/W R/W R W R/W R/W R R R/W UART_RBR UART_THR UART_IER UART_DLL UART_DLM UART_IIR UART_FCR UART_LCR UART_MCR UART_LSR UART_MSR UART_TOR 0x00 0x00 0x04 0x00 0x04 0x08 0x08 0x0C 0x10 0x14 0x18 0x1C Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register (Optional) Line Status Register MODEM Status Register (Optional) Time Out Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 Note: Real register address = 0xFFF8_0000+ (UART number - 1) * (0x0100) + offset Note: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times before send to APB bus. For example, when ARM CPU read register UARTn_BRR, ARM CPU will get UART0_RBR = {RBR[7:0], RBR[7:0], RBR[7:0], RBR[7:0]}. UART Receive Buffer Register (UART_RBR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined - 328 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 8-bit Received Data BITS DESCRIPTIONS [7:0] 8-bit Received Data By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first). UART Transmit Holding Register (UART_THR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_TH R 31 23 15 7 0x00 W Transmit Holding Register (DLAB = 0) Undefined 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 8-bit Transmitted Data BITS DESCRIPTIONS [7:0] 8-bit Transmitted Data By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first). - 329 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 UART Interrupt Enable Register (UART_IER) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 31 23 15 7 30 22 14 6 RESERVED 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 nDBGACK_E N 27 19 11 3 MSIE 26 18 10 2 RLSIE 25 17 9 1 THREIE 24 16 8 0 RDAIE BITS DESCRIPTIONS [31:5] Reserved ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held 1 = No matter what DBGACK is high or not, the UART receiver timer-out clock will not be held MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable 0 = Mask off Irpt_THRE 1 = Enable Irpt_THRE Receive Data Available Interrupt (Irpt_RDA) Enable and Time-out Interrupt (Irpt_TOUT) Enable 0 = Mask off Irpt_RDA and Irpt_TOUT 1 = Enable Irpt_RDA and Irpt_TOUT [4] nDBGACK_EN [3] MSIE [2] RLSIE [1] THREIE [0] RDAIE - 330 - W90P710 UART Divider Latch (Low Byte) Register (UART_DLL) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_DL L 31 23 15 7 0x00 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Baud Rate Divider (Low Byte) BITS DESCRIPTIONS [7:0] Baud Rate Divider (Low Byte) The low byte of the baud rate divider UART Divisor Latch (High Byte) Register (UART_DLM) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_DLM 31 23 15 7 0x04 30 22 14 6 R/W 29 21 13 5 Divisor Latch Register (MS) (DLAB = 1) 28 Reserved 20 Reserved 12 Reserved 4 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 Baud Rate Divider (High Byte) BITS DESCRIPTIONS [7:0] Baud Rate Divider (High Byte) The high byte of the baud rate divider - 331 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 - 332 - W90P710 This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} Note: This definition is different from 16550 UART Interrupt Identification Register (UART_IIR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_IIR 0x08 R Interrupt Identification Register 0x8181_8181 31 23 15 7 FMES 30 22 14 6 RFTLS 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 DMS 27 19 11 3 26 18 10 2 IID 25 17 9 1 24 16 8 0 NIP BITS DESCRIPTIONS FIFO Mode Enable Status [7] FMES This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enabling, this bit always shows the logical 1 when CPU is reading this register. RX FIFO Threshold Level Status [6:5] RFTLS These bits show the current setting of receiver FIFO threshold level (RTHO). The meaning of RTHO is defined in the following FCR description. DMA Mode Select [4] DMS The DMA function is not implemented in this version. When reading IIR, the DMS is always returned 0. Interrupt Identification The IID together with NIP indicates the current interrupt request from UART No Interrupt Pending There is no pending interrupt. [3:1] IID [0] NIP - 333 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 7.12.5.1 Interrupt Control Functions IIR [3:0] PRIORITY INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL ---1 0110 -Highest None Receiver Line Status (Irpt_RLS) Received Data Available (Irpt_RDA) Receiver FIFO Time-out (Irpt_TOUT) Transmitter Holing Register Empty (Irpt_THRE) MODEM Status (Irpt_MOS) None Overrun error, parity error, framing error, or break interrupt Receiver FIFO level is reached threshold -Reading the LSR Receiver FIFO drops below the threshold level 0100 Second 1100 Second Receiver FIFO is non-empty and no activities are occurred in the receiver FIFO during the TOR defined time duration Transmitter holding register empty Reading the RBR 0010 Third Reading the IIR (if source of interrupt is Irpt_THRE) or writing into the THR 0000 Fourth The CTS, DSR, or DCD bits are changing state or the RI Reading the MSR bit is changing from high to (optional) low. Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550 UART FIFO Control Register (UART_FCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_FCR 0x08 W FIFO Control Register Undefined 31 23 15 7 RFITL 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 DMS 26 18 10 2 TFR 25 17 9 1 RFR 24 16 8 0 FME RESERVED - 334 - W90P710 BITS DESCRIPTIONS RX FIFO Interrupt (Irpt_RDA) Trigger Level RFITL [7:6] [7:6] RFITL 00 01 10 11 [3] DMS Irpt_RDA Trigger Level (Bytes) 01 04 08 14 DMA Mode Select The DMA function is not implemented in this version. TX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. RX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. FIFO Mode Enable Because UART is always operating in the FIFO mode, writing this bit has no effect while reading always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not be programmed. [2] TFR [1] RFR [0] FME UART Line Control Register (UART_LCR) Register UART_LCR 31 23 15 7 DLAB Offset 0x0C 30 22 14 6 BCB R/W R/W Description Line Control Register 28 Reserved 21 13 5 SPE 20 Reserved 12 Reserved 4 EPE 3 PBE 2 NSB 1 WLS 0 11 10 9 8 19 18 17 16 27 26 25 Reset Value 0x0000_0000 24 29 - 335 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS Divider Latch Access Bit [7] DLAB 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM} Break Control Bit [6] BCB When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic. Stick Parity Enable [5] SPE 0 = Disable stick parity 1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit enable) is set. Even Parity Enable [4] EPE 0 = Odd number of logic 1's are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1's are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set. Parity Bit Enable [3] PBE 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. Number of "STOP bit" 0= One " STOP bit" is generated in the transmitted data [2] NSB 1= One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; Two " STOP bit" is generated when 6-, 7- and 8-bit word length is selected. Word Length Select WLS[1:0] [1:0] WLS 00 01 10 11 Character length 5 bits 6 bits 7 bits 8 bits - 336 - W90P710 UART Modem Control Register (UART_MCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_MCR 31 23 15 7 0x10 30 22 14 6 R/W 29 21 13 5 Modem Control Register (Optional) 28 20 12 4 LBME 27 Reserved 19 Reserved 11 Reserved 3 Reserve 2 Reserve 1 Reserved 10 9 18 17 26 25 0x0000_0000 24 16 8 0 DTR# Reserved BITS DESCRIPTIONS [31:5] Reserved - Loop-back Mode Enable 0 = Disable [4] LBME 1 = When the loop-back mode is enabled, the following signals are connected internally SOUT connected to SIN and SOUT pin fixed at logic 1 DTR# connected to DSR# and DTR# pin fixed at logic 1 [3:1] Reserved Complement version of DTR# (Data-Terminal-Ready) signal [0] DTR Writing 0x00 to MCR, the DTR# bit are set to logic 1's; Writing 0x0f to MCR, the DTR# bit are reset to logic 0's. UART Line Status Control Register (UART_LSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_LSR 0x14 R Line Status Register 0x6060_6060 - 337 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 ERR_RX BITS 30 22 14 6 TE 29 21 13 5 THRE 28 Reserved 20 Reserved 12 Reserved 4 BII 27 19 11 3 FEI DESCRIPTIONS 26 18 10 2 PEI 25 17 9 1 OEI 24 16 8 0 RFDR [31:8] Reserved - RX FIFO Error 0 = RX FIFO works normally [7] ERR_RX 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO. Transmitter Empty [6] TE 0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not empty. 1 = Both THR and TSR are empty. Transmitter Holding Register Empty 0 = THR is not empty. [5] THRE 1 = THR is empty. THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER [1]=1. Break Interrupt Indicator [4] BII This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU reads the contents of the LSR. Framing Error Indicator [3] FEI This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads the contents of the LSR. - 338 - W90P710 Continued. BITS DESCRIPTIONS Parity Error Indicator [2] PEI This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. Overrun Error Indicator [1] OEI An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads the contents of the LSR. RX FIFO Data Ready [0] RFDR 0 = RX FIFO is empty 1 = RX FIFO contains at least 1 received data word. LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR. LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt" (Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not suggested) UART Modem Status Register (UART_MSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_MSR 31 23 15 7 Reserved 0x18 30 22 14 6 Reserved R 29 21 13 5 MODEM Status Register (Optional) 28 Reserved 20 Reserved 12 Reserved 4 Reserved 0x0000_0000 25 17 9 1 DDSR 24 16 8 0 Reserved 27 19 11 3 Reserved 26 18 10 2 Reserved DSR# - 339 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:6] [5] [4:2] [1] [0] Reserved DSR# Reserved DDSR Reserved - Complement version of data set ready (DSR#) input (This bit is selected by IP) DSR# State Change (This bit is selected by IP) This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR. - Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing MSR is a null operation (not suggested). UART Time Out Register (UART_TOR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE UART_TOR 31 23 15 7 TOIE BITS 0x1C 30 22 14 6 R/W Time Out Register 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 3 TOIC DESCRIPTIONS 0x0000_0000 27 19 11 26 18 10 2 25 17 9 1 24 16 8 0 [31:8] [7] Reserved TOIE - Time Out Interrupt Enable The feature of receiver time out interrupt is enabled when TOR [7] = IER[0] = 1. Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears Irpt_TOUT. [6:0] TOIC - 340 - W90P710 7.12.6 High speed UART Controller The High Speed Universal Asynchronous Receiver/Transmitter (HS_UART) performs a serial-toparallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from the CPU. There are five types of interrupts, they are, transmitter FIFO empty interrupt, receiver threshold level reaching interrupt, line status interrupt (overrun error or parity error or framing error or break interrupt) ,time out interrupt, and Modem status interrupt . One 64-byte transmitter FIFO (TX_FIFO) and one 64-byte (plus 3-bit of error data per byte) receiver FIFO (RX_FIFO) has been built in to reduce the number of interrupts presented to the CPU. The CPU can completely read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt) found. The UART includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver needed. The equation is Baud Out = crystal clock / 16 * [Divisor + 2]. The UART includes the following features: Transmitter and receiver are buffered with a 64-byte FIFO each to reduce the number of interrupts presented to the CPU. Subset of MODEM control function(selected by IP) Fully programmable serial-interface characteristics: 5-, 6-, 7-, or 8-bit character Even, odd, or no-parity bit generation and detection 1-, 1&1/2, or 2-stop bit generation Baud rate generation False start bit detection Full-prioritized interrupt system controls Not support Loop back mode 7.12.6.1. High Speed UART Control Registers Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_RBR HSUART_THR HSUART_IER HSUART_DLL HSUART_DLM 0x00 0x00 0x04 0x00 0x04 R W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 R/W Interrupt Enable Register (DLAB = 0) R/W Divisor Latch Register (LS)(DLAB = 1) R/W Divisor Latch Register (MS)(DLAB = 1) - 341 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_IIR HSUART_FCR HSUART_LCR HSUART_MCR HSUART_LSR HSUART_MSR HSUART_TOR 0x08 0x08 0x0C 0x10 0x14 0x18 0x1C R W Interrupt Identification Register FIFO Control Register 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 R/W Line Control Register R/W Modem Control Register (Optional) R R Line Status Register MODEM Status Register (Optional) R/W Time Out Register Note: Real register address = 0xFFF8_0000+ (UART number - 1) * (0x0100) + offset NOTE: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times before send to APB bus. For example, when ARM CPU read register UART1_BRR, ARM CPU will get UART1_RBR = {RBR[7:0], _RBR[7:0], RBR[7:0], RBR[7:0]}. HSUART Receive Buffer Register (HSUART_RBR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 8-bit Received Data BITS DESCRIPTIONS [7:0] 8-bit Received Data By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first). - 342 - W90P710 HSUART Transmit Holding Register (HSUART_THR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 8-bit Transmitted Data BITS DESCRIPTIONS [7:0] 8-bit Transmitted Data By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first). HSUART Interrupt Enable Register (HSUART_IER) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 31 23 15 7 30 22 14 6 RESERVED 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 nDBGACK_EN 27 19 11 3 MSIE 26 18 10 2 RLSIE 25 17 9 1 THREIE 24 16 8 0 RDAIE - 343 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:5] Reserved ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held 1 = No matter what DBGACK is high or not, the UART receiver timerout clock will not be held MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable 0 = Mask off Irpt_THRE 1 = Enable Irpt_THRE Receive Data Available Interrupt (Irpt_RDA) Enable and Time-out Interrupt (Irpt_TOUT) Enable 0 = Mask off Irpt_RDA and Irpt_TOUT 1 = Enable Irpt_RDA and Irpt_TOUT [4] nDBGACK_EN [3] MSIE [2] RLSIE [1] THREIE [0] RDAIE HSUART Divider Latch (Low Byte) Register (HSUART_DLL) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_DL L 31 23 15 7 30 22 14 6 0x00 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Baud Rate Divider (Low Byte) - 344 - W90P710 BITS DESCRIPTIONS [31:8] [7:0] Reserved Baud Rate Divisor (Low Byte) The low byte of the baud rate divider HSUART Divisor Latch (High Byte) Register (HSUART_DLM) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_DLM 0x04 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Baud Rate Divider (High Byte) BITS DESCRIPTIONS [31:8] [7:0] Reserved Baud Rate Divisor (High Byte) The high byte of the baud rate divider This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} HSUART Interrupt Identification Register (HSUART_IIR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_IIR 0x08 R Interrupt Identification Register 0x8181_8181 - 345 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 FMES 30 22 14 6 RFTLS 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 DMS 27 19 11 3 26 18 10 2 IID 25 17 9 1 24 16 8 0 NIP BITS DESCRIPTIONS [31:8] Reserved FIFO Mode Enable Status [7] FMES This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable, this bit always shows the logical 1 when CPU is reading this register. RX FIFO Threshold Level Status [6:5] RFTLS These bits show the current setting of receiver FIFO threshold level (RTHO). The meaning of RTHO is defined in the following FCR description. DMA Mode Select [4] DMS The DMA function is not implemented in this version. When reading IIR, the DMS is always returned 0. Interrupt Identification [3:1] IID The IID together with NIP indicates the current interrupt request from UART. No Interrupt Pending There is no pending interrupt. [0] NIP - 346 - W90P710 Interrupt Control Functions IIR [3:0] PRIORIT Y INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL ---1 0110 -Highest None Receiver Line Status (Irpt_RLS) Received Data Available (Irpt_RDA) None Overrun error, parity error, framing error, or break interrupt Receiver FIFO threshold level is reached Receiver FIFO is nonempty and no activities are occurred in the receiver FIFO during the TOR defined time duration Transmitter register empty holding -Reading the LSR Receiver FIFO drops below the threshold level 0100 Second 1100 Second Receiver FIFO Timeout (Irpt_TOUT) Reading the RBR 0010 Third Transmitter Holing Register Empty (Irpt_THRE) Reading the IIR (if source of interrupt is Irpt_THRE) or writing into the THR 0000 Fourth MODEM Status (Irpt_MOS) The CTS bits are changing Reading the MSR state . (optional) Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550. HSUART FIFO Control Register (HSUART_FCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_FCR 31 23 15 7 30 22 14 6 0x08 W 29 21 13 5 28 FIFO Control Register 27 Reserved 20 Reserved 12 Reserved 4 3 DMS 2 TFR 1 RFR 11 10 9 19 18 17 26 25 Undefined 24 16 8 0 FME RFITL - 347 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:8] Reserved RX FIFO Interrupt (Irpt_RDA) Trigger Level RFITL 0000 0001 0010 Irpt_RDA Trigger Level (Bytes) 01 04 08 14 30 46 62 62 [7:4] RFITL 0011 0100 0101 0110 others [3] DMS DMA Mode Select The DMA function is not implemented in this version. TX FIFO Reset [2] TFR Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. RX FIFO Reset [1] RFR Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. FIFO Mode Enable [0] FME Because UART is always operating in the FIFO mode, writing this bit has no effect while reading always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not be programmed. - 348 - W90P710 HSUART Line Control Register (HSUART_LCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_LCR BITS 0x0C R/W Line Control Register DESCRIPTIONS 0x0000_0000 [31:8] [7] Reserved DLAB [6] BCB [5] SPE [4] EPE [3] PBE [2] NSB Divider Latch Access Bit 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM}. Break Control Bit When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic. Stick Parity Enable 0 = Disable stick parity 1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit enable) is set. Even Parity Enable 0 = Odd number of logic 1's are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1's are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set. Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. Number of "STOP bit" 0= One " STOP bit" is generated in the transmitted data 1= One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; Two " STOP bit" is generated when 6-, 7- and 8-bit word length is selected. Word Length Select WLS[1:0] Character length 5 bits 6 bits 7 bits 8 bits 00 01 10 11 [1:0] WLS - 349 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 DLAB 30 22 14 6 BCB 29 21 13 5 SPE 28 Reserved 20 Reserved 12 Reserved 4 EPE 27 19 11 3 PBE 26 18 10 2 NSB 25 17 9 1 WLS 24 16 8 0 HSUART Modem Control Register (HSUART_MCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 LBME 27 19 11 3 26 18 10 2 25 17 9 1 RTS 24 16 8 0 Reserved Reserved DESCRIPTIONS BITS [31:5] Reserved Loop-back Mode Enable 0 = Disable 1 = When the loop-back mode is enabled, the following signals are connected internally: SOUT connected to SIN and SOUT pin fixed at logic 1 RTS# connected to CTS# and RTS# pin fixed at logic 1 [4] LBME - 350 - W90P710 Continued. BITS DESCRIPTIONS [3:2] Reserved Complement version of RTS# (Request-To-Send) signal [1] RTS# Writing 0x00 to MCR, RTS# bit are set to logic 1's; Writing 0x0f to MCR, RTS# bit are reset to logic 0's. [0] Reserved - HSUART Line Status Control Register (HSUART_LSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_LSR 0x14 R Line Status Register 0x6060_6060 31 23 15 7 ERR_RX 30 22 14 6 TE 29 21 13 5 THRE 28 Reserved 20 Reserved 12 Reserved 4 BII 27 19 11 3 FEI 26 18 10 2 PEI 25 17 9 1 OEI 24 16 8 0 RFDR BITS DESCRIPTIONS [31:8] Reserved RX FIFO Error 0 = RX FIFO works normally [7] ERR_RX 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO. Transmitter Empty [6] TE 0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not empty. 1 = Both THR and TSR are empty. - 351 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued. BITS DESCRIPTIONS Transmitter Holding Register Empty 0 = THR is not empty. [5] THRE 1 = THR is empty. THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER [1]=1. Break Interrupt Indicator [4] BII This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU reads the contents of the LSR. Framing Error Indicator [3] FEI This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads the contents of the LSR. Parity Error Indicator [2] PEI This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. Overrun Error Indicator [1] OEI An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads the contents of the LSR. RX FIFO Data Ready [0] RFDR 0 = RX FIFO is empty 1 = RX FIFO contains at least 1 received data word. LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR. LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt" (Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not suggested). - 352 - W90P710 HSUART Modem Status Register (HSUART_MSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_MSR 31 23 15 7 30 22 14 6 0x18 R 29 21 13 5 MODEM Status Register (Optional) 28 Reserved 20 Reserved 12 Reserved 4 CTS# 3 2 Reserved 0x0000_0000 25 17 9 1 24 16 8 0 DCTS 27 19 11 26 18 10 Reserved BITS DESCRIPTIONS [31:5] [4] [3:1] Reserved CTS# Reserved Complement version of clear to send (CTS#) input (This bit is selected by IP) CTS# State Change (This bit is selected by IP) This bit is set whenever CTS# input has changed state, and it will be reset if the CPU reads the MSR. [0] DCTS Whenever any of MSR [0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing MSR is a null operation (not suggested). HSUART Time Out Register (HSUART_TOR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_TOR 0x1C R/W Time Out Register 0x0000_0000 - 353 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 TOIE 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 TOIC 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:8] [7] Reserved TOIE Time Out Interrupt Enable The feature of receiver time out interrupt is enabled only when TOR [7] = IER[0] = 1. Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears Irpt_TOUT. [6:0] TOIC - 354 - W90P710 7.13 Timer/Watchdog Controller 7.13.1 General Timer Controller The timer module includes two channels, TIMER0 and TIMER1, which allow you to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information. The timer can generate an interrupt signal upon timeout, or provide the current value of count during operation. The general TIMER Controller includes the following features AMBA APB interface compatible Two channels with a 8-bit presale counter/24-bit down counter and an interrupt request each Independent clock source for each channel Maximum uninterrupted time = (1 / 25 MHz) * (256) * (2^24), if TCLK = 25 MHz 7.13.2 Watchdog Timer 7.13.3 Timer Control Registers Map R: read only, W: write only, R/W: both read and write REGISTER ADDRESS R/W/C DESCRIPTION RESET VALUE TCSR0 TCSR1 TICR0 TICR1 TDR0 TDR1 TISR WTCR 0xFFF8_10000 0xFFF8_10004 0xFFF8_10008 0xFFF8_1000C 0xFFF8_10010 0xFFF8_10014 0xFFF8_10018 0xFFF8_1001C R/W R/W R/W R/W R R R/W R/W Timer Control and Status Register 0 Timer Control and Status Register 1 Timer Initial Control Register 0 Timer Initial Control Register 1 Timer Data Register 0 Timer Data Register 1 Timer Interrupt Status Register Watchdog Timer Control Register 0x0000_0005 0x0000_0005 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0400 Timer Control Register 0/1 (TCSR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TCSR0 TCSR1 0xFFF8_1000 0xFFF8_1004 R/W R/W Timer Control and Status Register 0 Timer Control and Status Register 1 0x0000_0005 0x0000_0005 - 355 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 nDBGACK_EN 23 30 CEN 22 29 IE 21 28 27 26 CRST 18 25 CACT 17 24 Reserved 16 MODE[1:0] 20 Reserved 19 15 14 13 12 Reserved 11 10 9 8 7 6 5 4 3 2 1 0 PRESCALE[7:0] BITS DESCRIPTIONS ICE debug mode acknowledge enable [31] nDBGACK_EN 0 = When DBGACK is high, the TIMER counter will be held 1 = No matter DBGACK is high or not, the TIMER counter will not be held Counter Enable [30] CEN 0 = Stops/Suspends counting 1 = Starts counting Interrupt Enable 0 = Disable TIMER Interrupt. [29] IE 1 = Enable TIMER Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter decrements to zero. Timer Operating Mode MODE 00 Timer Operating Mode The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared then. The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. Reserved. [28:27] MODE 01 10 11 - 356 - W90P710 Continued BITS DESCRIPTIONS Counter Reset Set this bit will reset the TIMER counter, and also force CEN to 0. [26] CRST 0 = No effect. 1 = Reset Timer's prescale counter, internal 24-bit counter and CEN. Timer is in Active [25] CACT This bit indicates the counter status of timer. 0 = Timer is not active. 1 = Timer is in active. [24:8] [7:0] Reserved PRESCALE Reserved Prescale Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling. Timer Initial Count Register 0/1 (TICR0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TICR0 TICR1 0xFFF8_1008 0xFFF8_100C R/W R/W Timer Initial Control Register 0 Timer Initial Control Register 1 0x0000_0000 0x0000_0000 31 30 29 28 Reserved 27 26 25 24 23 22 21 20 19 18 17 16 TIC [23:16] 15 14 13 12 TIC [15:8] 7 6 5 4 TIC [7:0] 3 2 1 0 11 10 9 8 - 357 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:24] Reserved Reserved Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. NOTE1: Never write 0x0 in TIC, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. [23:0] TIC Timer Data Register 0/1 (TDR0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TDR0 TDR1 0xFFF8_10010 0xFFF8_10014 R R Timer Data Register 0 Timer Data Register 1 0x0000_0000 0x0000_0000 31 30 29 28 Reserved 27 26 25 24 23 22 21 20 19 18 17 16 TDR [23:16] 15 14 13 12 11 10 9 8 TDR [15:8] 7 6 5 4 TDR [7:0] 3 2 1 0 BITS DESCRIPTIONS [31:24] Reserved Reserved Timer Data Register The current count is registered in this 24-bit value. NOTE: Software can read a correct current value on this register only when CEN = 0, or the value represents here could not be a correct one. [23:0] TDR - 358 - W90P710 Timer Interrupt Status Register (TISR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TISR 0xFFF8_1018 R/W Timer Interrupt Status Register 0x0000_0000 31 30 29 28 27 Reserved 26 25 24 23 22 21 20 19 Reserved 18 17 16 15 14 13 12 11 Reserved 10 9 8 7 6 5 Reserved 4 3 2 1 TIF1 0 TIF0 BITS DESCRIPTIONS Timer Interrupt Flag 1 This bit indicates the interrupt status of Timer channel 1. [1] TIF1 0 = It indicates that the Timer 1 dose not countdown to zero yet. 1 = It indicates that the counter of Timer 1 has decremented to zero. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Timer Interrupt Flag 0 This bit indicates the interrupt status of Timer channel 0. [0] TIF0 0 = It indicates that the Timer 0 dose not countdown to zero yet. 1 = It indicates that the counter of Timer 0 has decremented to zero. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Watchdog Timer Control Register (WTCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE WTCR 0xFFF8_101C R/W Watchdog Timer Control Register 0x0000_0400 - 359 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 30 29 28 27 Reserved 23 22 21 20 19 Reserved 15 14 13 Reserved 7 WTE BITS 26 25 24 18 17 16 12 11 10 9 8 WTCLK nDBGACK_EN WTTME 4 3 WTIF DESCRIPTIONS 6 WTIE 5 WTIS 2 WTRF 1 WTRE 0 WTR [31:11] Reserved Reserved Watchdog Timer Clock This bit is used for deciding whether the Watchdog timer clock input is divided by 256 or not. Clock source of Watchdog timer is Crystal input. 0 = Using original clock input 1 = The clock input will be divided by 256 NOTE: When WTTME = 1, set this bit has no effect on WDT clock (using original clock input). ICE debug mode acknowledge enable 0 = When DBGACK is high, the Watchdog timer counter will be held 1 = No matter DBGACK is high or not, the Watchdog timer counter will not be held Watchdog Timer Test Mode Enable For reasons of efficiency, the 26-bit counter within the Watchdog timer is considered as two independent 13-bit counters in the test mode. They are operated concurrently and separately during the test. This approach can save a lot of time spent in the test. When the 13bit counter overflows, a Watchdog timer interrupt is generated. 0 = Put the Watchdog timer in normal operating mode 1 = Put the Watchdog timer in test mode Watchdog Timer Enable 0 = Disable the Watchdog timer (This action will reset the internal counter) 1 = Enable the Watchdog timer [10] WTCLK [9] nDBGACK_EN [8] WTTME [7] WTE - 360 - W90P710 Continued BITS DESCRIPTIONS Watchdog Timer Interrupt Enable [6] WTIE 0 = Disable the Watchdog timer interrupt 1 = Enable the Watchdog timer interrupt Watchdog Timer Interval Select These two bits select the interval for the Watchdog timer. No matter which interval is chosen, the reset timeout is always occurred 512 WDT clock cycles later than the interrupt timeout. WTIS [5:4] WTIS 00 01 10 11 Interrupt Timeout 214 clocks 216 clocks 218 clocks 220 clocks Reset Timeout 214 + 1024 clocks 216 + 1024 clocks 218 + 1024 clocks 220 + 1024 clocks Real Time Interval (CLK=15MHz/256) 0.28 sec. 1.12 sec. 4.47 sec. 17.9 sec. Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. 0 = Watchdog timer interrupt does not occur 1 = Watchdog timer interrupt occurs NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it up manually. If WTRE is disabled, then the Watchdog timer has no effect on this bit. 0 = Watchdog timer reset does not occur 1 = Watchdog timer reset occurs NOTE: This bit is read only, but can be cleared by writing 1 to this bit. [3] WTIF [2] WTRF - 361 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS Watchdog Timer Reset Enable [1] WTRE Setting this bit will enable the Watchdog timer reset function. 0 = Disable Watchdog timer reset function 1 = Enable Watchdog timer reset function Watchdog Timer Reset This bit brings the Watchdog timer into a known state. It helps reset the Watchdog timer before a timeout situation occurring. Failing to set WTR before timeout will initiates an interrupt if WTIE is set. If the WTRE bit is set, Watchdog timer reset will be occurred 512 WDT clock cycles after timeout. This bit is self-clearing. 0 = No operation 1 = Reset the contents of the Watchdog timer [0] WTR - 362 - W90P710 7.14 Advanced Interrupt Controller An interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception is occurred when the nIRQ input is asserted. Similarly, the FIQ exception is occurred when the nFIQ input is asserted. The FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible to ignore the FIQ and the IRQ by setting the F and I bits in the current program status register (CPSR). The W90P710 incorporates the advanced interrupt controller (AIC) that is capable of dealing with the interrupt requests from a total of 32 different sources. Currently, 31 interrupt sources are defined. Each interrupt source is uniquely assigned to an interrupt channel. For example, the watchdog timer interrupt is assigned to channel 1. The AIC implements a proprietary eight-level priority scheme that differentiates the available 31 interrupt sources into eight priority levels. Interrupt sources within the priority level 0 have the highest priority and the priority level 7 has the lowest. To work this scheme properly, you must specify a certain priority level to each interrupt source during power-on initialization; otherwise, the system shall behave unexpectedly. Within each priority level, interrupt source that is positioned in a lower channel has a higher priority. Interrupt source that is active, enabled, and positioned in the lowest channel within the priority level 0 is promoted to the FIQ. Interrupt sources within the priority levels other than 0 can petition for the IRQ. The IRQ can be preempted by the occurrence of the FIQ. Interrupt nesting is performed automatically by the AIC. Though interrupt sources originated from the W90P710 itself are intrinsically high-level sensitive, the AIC can be configured as either low-level sensitive, high-level sensitive, negative-edge triggered, or positive-edge triggered to each interrupt source. When the W90P710 is put in the test mode, all interrupt sources must be configured as positive-edge triggered. The advanced interrupt controller includes the following features: AMBA APB bus interface External interrupts can be programmed as either edge-triggered or level-sensitive External interrupts can be programmed as either low-active or high-active Has flags to reflect the status of each interrupt source Individual mask for each interrupt source Proprietary 8-level interrupt scheme to ease the burden from the interrupt Priority methodology is adopted to allow for interrupt daisy-chaining Automatically masking out the lower priority interrupt during interrupt nesting Automatically clearing the interrupt flag when the external interrupt source is programmed to be edge-triggered - 363 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.14.1 Interrupt Sources Table 7.14.1 W90P710 Interrupt Sources PRIORITY NAME MODE SOURCE 1 (Highest) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 WDT_INT nIRQ0 nIRQ1 nIRQ2 nIRQ3 AC97_INT LCD_INT RTC_INT UART_INT0 UART_INT1 UART_INT2 UART_INT3 T_INT0 T_INT1 USBH_INT0 USBH_INT1 EMCTX_INT EMCRX_INT GDMA_INT0 GDMA_INT1 SDIO_INT USBD_INT SC_INT0 SC_INT1 I2C_INT0 I2C_INT1 SSP_INT PWM _INT KPI_INT PS2_INT IRQ45_INT Positive Level Programmable Programmable Programmable Programmable Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Positive Level Watch Dog Timer Interrupt External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 AC97 Interrupt LCD Controller Interrupt RTC Interrupt UART Interrupt0 UART Interrupt1 UART Interrupt2 UART Interrupt3 Timer Interrupt 0 Timer Interrupt 1 USB Host Interrupt 0 USB Host Interrupt 1 EMC TX Interrupt EMC RX Interrupt GDMA Channel Interrupt 0 GDMA Channel Interrupt 1 SDIO Interrupt USB Device Interrupt Smart Card Interrupt 0 Smart Card Interrupt 1 I2C Interrupt0 I2C Interrupt1 SSP Interrupt PWM Timer interrupt Keypad Interrupt PS2 Interrupt GPIO0 & GPIO70 Interrupt - 364 - W90P710 AIC Functional Description Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used, priority determination must be carried out by software. When the Interrupt Priority Encoding Register (AIC_IPER) is read, it will return an integer representing the channel that is active and having the highest priority. This integer is equivalent to multiplied by 4 (shifted left two bits to word-align it) such that it may be used directly to index into a branch table to select the appropriate interrupt service routine vector. Priority Controller An 8-level priority encoder controls the NIRQ line. Each interrupt source belongs to priority group between of 0 to 7. Group 0 has the highest priority and group 7 the lowest. When more than one unmasked interrupt channels are active at a time, the interrupt with the highest priority is serviced first. If all active interrupts have equal priority, the interrupt with the lowest interrupt source number is serviced first. The current priority level is defined as the priority level of the interrupt with the highest priority at the time the register AIC_IPER is read. In the case when a higher priority unmasked interrupt occurs while an interrupt already exits, there are two possible outcomes depending on whether the AIC_IPER has been read. If the processor has already read the AIC_IPER and caused the NIRQ line to be deasserted, then the NIRQ line is reasserted. When the processor has enabled nested interrupts and reads the AIC_IPER again, it reads the new, higher priority interrupt vector. At the same time, the current priority level is updated to the higher priority. If the AIC_IPER has not been read after the NIRQ line has been asserted, then the processor will read the new higher priority interrupt vector in the AIC_IPER register and the current priority level is updated. When the End of Service Command Register (AIC_EOSCR) is written, the current interrupt level is updated with the last stored interrupt level from the stack (if any). Therefore, at the end of a higher priority interrupt, the AIC returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted. Interrupt Handling When the IRQ line is asserted, the interrupt handler must read the AIC_IPER as soon as possible. This can de-assert the NIRQ request to the processor and clears the interrupt if it is programmed to be edge triggered. This allows the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. The AIC_EOSCR (End of Service Command Register) must be written at the end of the interrupt service routine. This permits pending interrupts to be serviced. - 365 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled individually by using the command registers AIC_MECR and AIC_MDCR. The status of interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt doesn't affect the servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources (including FIQ) can be individually set or clear by respectively writing to the registers AIC_SSCR and AIC_SCCR when they are programmed to be edge triggered. This feature of the AIC is useful in auto-testing or software debugging. Fake Interrupt When the AIC asserts the NIRQ line, the processor enters interrupt mode and the interrupt handler reads the AIC_IPER, it may happen that AIC de-asserts the NIRQ line after the processor has taken into account the NIRQ assertion and before the read of the AIC_IPER. This behavior is called a fake interrupt. The AIC is able to detect these fake interrupts and returns all zero when AIC_IPER is read. The same mechanism of fake interrupt occurs if the processor reads the AIC_IPER (application software or ICE) when there is no interrupt pending. The current priority level is not updated in this situation. Hence, the AIC_EOSCR shouldn't be written. ICE/Debug Mode This mode allows reading of the AIC_IPER without performing the associated automatic operations. This is necessary when working with a debug system. When an ICE or debug monitor reads the AIC user interface, the AIC_IPER can be read. This has the following consequences in normal mode: If there is no enabled pending interrupt, the fake vector will be returned. If an enabled interrupt with a higher priority than the current one is pending, it will be stacked. In the second case, an End-of-Service command would be necessary to restore the state of the AIC. This operation is generally not performed by the debug system. Therefore, the debug system would become strongly intrusive, and could cause the application to enter an undesired state. This can be avoided by using ICE/Debug Mode. When this mode is enabled. The AIC performs interrupt stacking only when a write access is performed on the AIC_IPER. Hence, the interrupt service routine must write to the AIC_IPER (any value) just after reading it. When AIC_IPER is written, the new status of AIC, including the value of interrupt source number register (AIC_ISNR), is updated with the value that is kept at previous reading of AIC_IPER The debug system must not write to the AIC_IPER as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are performed according to the mode: - 366 - W90P710 ACTION NORMAL MODE ICE/DEBUG MODE Calculate active interrupt Read AIC_IPER Read AIC_IPER Read AIC_IPER Write AIC_IPER Write AIC_IPER Determine and return the vector of the active interrupt Read AIC_IPER Push on internal stack the current priority level Acknowledge the interrupt (Note 1) No effect (Note 2) Notes: Read AIC_IPER Read AIC_IPER Read AIC_IPER NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive. Note that software which has been written and debugged using this mode will run correctly in normal mode without modification. However, in normal mode writing to AIC_IPER has no effect and can be removed to optimize the code 7.14.2 AIC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 AIC_SCR2 AIC_SCR3 AIC_SCR4 AIC_SCR5 AIC_SCR6 AIC_SCR7 AIC_SCR8 AIC_SCR9 AIC_SCR10 AIC_SCR11 AIC_SCR12 AIC_SCR13 AIC_SCR14 AIC_SCR15 0xFFF8_2004 R/W Source Control Register 1 0xFFF8_2008 R/W Source Control Register 2 0xFFF8_200C R/W Source Control Register 3 0xFFF8_2010 R/W Source Control Register 4 0xFFF8_2014 R/W Source Control Register 5 0xFFF8_2018 R/W Source Control Register 6 0xFFF8_201C R/W Source Control Register 7 0xFFF8_2020 R/W Source Control Register 8 0xFFF8_2024 R/W Source Control Register 9 0xFFF8_2028 R/W Source Control Register 10 0xFFF8_202C R/W Source Control Register 11 0xFFF8_2030 R/W Source Control Register 12 0xFFF8_2034 R/W Source Control Register 13 0xFFF8_2038 R/W Source Control Register 14 0xFFF8_203C R/W Source Control Register 15 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 - 367 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 AIC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR16 AIC_SCR17 AIC_SCR18 AIC_SCR19 AIC_SCR20 AIC_SCR21 AIC_SCR22 AIC_SCR23 AIC_SCR24 AIC_SCR25 AIC_SCR26 AIC_SCR27 AIC_SCR28 AIC_SCR29 AIC_SCR30 AIC_SCR31 AIC_IRSR AIC_IASR AIC_ISR AIC_IPER AIC_ISNR AIC_IMR AIC_OISR AIC_MECR AIC_MDCR AIC_SSCR AIC_SCCR AIC_TEST 0xFFF8_2040 R/W Source Control Register 16 0xFFF8_2044 R/W Source Control Register 17 0xFFF8_2048 R/W Source Control Register 18 0xFFF8_204C R/W Source Control Register 19 0xFFF8_2050 R/W Source Control Register 20 0xFFF8_2054 R/W Source Control Register 21 0xFFF8_2058 R/W Source Control Register 22 0xFFF8_205C R/W Source Control Register 23 0xFFF8_2060 R/W Source Control Register 24 0xFFF8_2064 R/W Source Control Register 25 0xFFF8_2068 R/W Source Control Register 26 0xFFF8_206C R/W Source Control Register 27 0xFFF8_2070 R/W Source Control Register 28 0xFFF8_2074 R/W Source Control Register 29 0xFFF8_2078 R/W Source Control Register 30 0xFFF8_207C R/W Source Control Register 31 0xFFF8_2100 0xFFF8_2104 0xFFF8_2108 0xFFF8_210C 0xFFF8_2110 0xFFF8_2114 0xFFF8_2118 0xFFF8_2120 0xFFF8_2124 0xFFF8_2128 0xFFF8_212C 0xFFF8_2200 R R R R R R R W W W W W W Interrupt Raw Status Register Interrupt Active Status Register Interrupt Status Register Interrupt Priority Encoding Register Interrupt Source Number Register Interrupt Mask Register Output Interrupt Status Register Mask Enable Command Register Mask Disable Command Register Source Set Command Register Source Clear Command Register End of Service Command Register ICE/Debug mode Register 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined Undefined Undefined Undefined Undefined Undefined AIC_EOSCR 0xFFF8_2130 - 368 - W90P710 AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR31) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 AIC_SCR2 0xFFF8_2004 R/W Source Control Register 1 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 0x0000_0047 AIC_SCR28 AIC_SCR29 AIC_SCR30 AIC_SCR31 31 23 15 7 0xFFF8_2070 R/W Source Control Register 28 0xFFF8_2074 R/W Source Control Register 29 0xFFF8_2078 R/W Source Control Register 30 0xFFF8_207C R/W Source Control Register 31 30 22 14 6 29 21 13 5 28 20 12 4 RESERVED DESCRIPTIONS 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 26 18 10 2 25 17 9 1 PRIORITY 24 16 8 0 27 19 11 3 RESERVED RESERVED RESERVED SRCTYPE BITS [31:8] Reserved Reserved Interrupt Source Type Whether an interrupt source is considered active or not by the AIC is subject to the settings of this field. Interrupt sources other than nIRQ0, nIRQ1, nIRQ2, nIRQ3, should be configured as level sensitive during normal operation unless in the testing situation. [7:6] SRCTYPE SRCTYPE [7:6] 0 0 1 1 0 1 0 1 Interrupt Source Type Low-level Sensitive High-level Sensitive Negative-edge Triggered Positive-edge Triggered - 369 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS [5:3] Reserved Reserved Priority Level Every interrupt source must be assigned a priority level during initiation. Among them, priority level 0 has the highest priority and priority level 7 the lowest. Interrupt sources with priority level 0 are promoted to FIQ. Interrupt sources with priority level other than 0 belong to IRQ. For interrupt sources of the same priority level that located in the lower channel number has higher priority. [2:0] PRIORITY AIC Interrupt Raw Status Register (AIC_IRSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_IRSR 31 IRS31 23 IRS23 15 IRS15 7 IRS7 0xFFF8_2100 30 IRS30 22 IRS22 14 IRS14 6 IRS6 29 R Interrupt Raw Status Register 28 IRS28 20 IRS20 12 IRS12 4 IRS4 27 IRS27 19 IRS19 11 IRS11 3 IRS3 26 IRS26 18 IRS18 10 IRS10 2 IRS2 25 0x0000_0000 24 IRS24 16 IRS16 8 IRS8 0 RESERVED IRS29 21 IRS21 13 IRS13 5 IRS5 IRS25 17 IRS17 9 IRS9 1 IRS1 BITS DESCRIPTIONS This register records the intrinsic state within each interrupt channel. IRSx: Interrupt Status Indicate the intrinsic status of the corresponding interrupt source 0 = Interrupt channel is in the voltage level 0 1 = Interrupt channel is in the voltage level 1 [0] Reserved Reserved [31:1] IRSx - 370 - W90P710 AIC Interrupt Active Status Register (AIC_IASR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_IASR 31 IAS31 23 IAS23 15 IAS15 7 IAS7 0xFFF8_2104 30 IAS30 22 IAS22 14 IAS14 6 IAS6 29 R Interrupt Active Status Register 28 IAS28 20 IAS20 12 IAS12 4 IAS4 27 IAS27 19 IAS19 11 IAS11 3 IAS3 26 IAS26 18 IAS18 10 IAS10 2 IAS2 25 0x0000_0000 24 IAS24 16 IAS16 8 IAS8 0 RESERVED IAS29 21 IAS21 13 IAS13 5 IAS5 IAS25 17 IAS17 9 IAS9 1 IAS1 BITS DESCRIPTIONS This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting. [31:1] IASx IASx: Interrupt Active Status Indicate the status of the corresponding interrupt source 0 = Corresponding interrupt channel is inactive 1 = Corresponding interrupt channel is active [0] Reserved Reserved AIC Interrupt Status Register (AIC_ISR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_ISR 0xFFF8_2108 R Interrupt Status Register 0x0000_0000 - 371 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 IS31 23 IS23 15 IS15 7 IS7 BITS 30 IS30 22 IS22 14 IS14 6 IS6 29 IS29 21 IS21 13 IS13 5 IS5 28 IS28 20 IS20 12 IS12 4 IS4 27 IS27 19 IS19 11 IS11 3 IS3 DESCRIPTIONS 26 IS26 18 IS18 10 IS10 2 IS2 25 IS25 17 IS17 9 IS9 1 IS1 24 IS24 16 IS16 8 IS8 0 RESERVED [31:1] ISx This register identifies those interrupt channels whose are both active and enabled. ISx: Interrupt Status Indicates the status of corresponding interrupt channel 0 = Two possibilities: (1) The corresponding interrupt channel is inactive no matter whether it is enabled or disabled; (2) It is active but not enabled 1 = Corresponding interrupt channel is both active and enabled (can assert an interrupt) Reserved [0] Reserved AIC IRQ Priority Encoding Register (AIC_IPER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_IPER 31 0 23 0 15 0 7 0 0xFFF8_210C 30 0 22 0 14 0 6 29 0 21 0 13 0 5 R Interrupt Priority Encoding Register 28 0 20 0 12 0 4 VECTOR 27 0 19 0 11 0 3 26 0 18 0 10 0 2 25 0 17 0 9 0 1 0 0x0000_0000 24 0 16 0 8 0 0 0 - 372 - W90P710 BITS DESCRIPTIONS [6:2] Vector When the AIC generates the interrupt, VECTOR represents the interrupt channel number that is active, enabled, and has the highest priority. If the representing interrupt channel possesses a priority level 0, then the interrupt asserted is FIQ; otherwise, it is IRQ. The value of VECTOR is copied to the register AIC_ISNR thereafter by the AIC. This register was restored a value 0 after it was read by the interrupt handler. This register can help indexing into a branch table to quickly jump to the corresponding interrupt service routine. VECTOR [6:2]: Interrupt Vector 0 = no interrupt occurs 1 ~ 31 = representing the interrupt channel that is active, enabled, and having the highest priority [0] Reserved Reserved AIC Interrupt Source Number Register (AIC_ISNR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_ISNR 31 0 23 0 15 0 7 0 0xFFF8_2110 30 0 22 0 14 0 6 0 29 0 21 0 13 0 5 0 R Interrupt Source Number Register 28 0 20 0 12 0 4 27 0 19 0 11 0 3 26 0 18 0 10 0 2 IRQID 25 0 17 0 9 0 1 0x0000_0000 24 0 16 0 8 0 0 BITS DESCRIPTIONS [31:5] Reserved Reserved The purpose of this register is to record the interrupt channel number that is active, enabled, and has the highest priority. IRQID [4:0]: IRQ Identification Stands for the interrupt channel number [4:0] IRQID - 373 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 AIC Interrupt Mask Register (AIC_IMR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_IMR 31 IM31 23 IM23 15 IM15 7 IM7 BITS 0xFFF8_2114 30 IM30 22 IM22 14 IM14 6 IM6 29 R Interrupt Mask Register 28 IM28 20 IM20 12 IM12 4 IM4 27 IM27 19 IM19 11 IM11 3 IM3 DESCRIPTIONS 0x0000_0000 26 IM26 18 IM18 10 IM10 2 IM2 25 IM25 17 IM17 9 IM9 1 IM1 24 IM24 16 IM16 8 IM8 0 RESERVED IM29 21 IM21 13 IM13 5 IM5 [31:1] IM x IMx: Interrupt Mask This bit determines whether the corresponding interrupt channel is enabled or disabled. Every interrupt channel can be active no matter whether it is enabled or disabled. If an interrupt channel is enabled, it does not definitely mean it is active. Every interrupt channel can be authorized by the AIC only when it is both active and enabled. 0 = Corresponding interrupt channel is disabled 1 = Corresponding interrupt channel is enabled Reserved [0] Reserved AIC Output Interrupt Status Register (AIC_OISR) Register AIC_OISR Address 0xFFF8_2118 R/W R Description Output Interrupt Status Register Reset Value 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 IRQ 24 16 8 0 FIQ RESERVED RESERVED RESERVED RESERVED - 374 - W90P710 The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred. BITS DESCRIPTIONS [31:2] Reserved Reserved IRQ [1]: Interrupt Request [1] IRQ 0 = nIRQ line is inactive. 1 = nIRQ line is active. FIQ [0]: Fast Interrupt Request [0] FIQ 0 = nFIQ line is inactive. 1 = nFIQ line is active AIC Mask Enable Command Register (AIC_MECR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_MECR 31 MEC31 23 MEC23 15 MEC15 7 MEC7 BITS 0xFFF8_2120 30 MEC30 22 MEC22 14 MEC14 6 MEC6 29 W Mask Enable Command Register 28 MEC28 20 MEC20 12 MEC12 4 MEC4 27 MEC27 19 MEC19 11 MEC11 3 MEC3 DESCRIPTIONS Undefined 25 MEC25 17 MEC17 9 MEC9 1 MEC1 24 MEC24 16 MEC16 8 MEC8 0 RESERVED 26 MEC26 18 MEC18 10 MEC10 2 MEC2 MEC29 21 MEC21 13 MEC13 5 MEC5 MEC x: Mask Enable Command [31:1] MEC x 0 = No effect 1 = Enables the corresponding interrupt channel [0] Reserved Reserved - 375 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 AIC Mask Disable Command Register (AIC_MDCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_MDCR 31 MDC31 23 MDC23 15 MDC15 7 MDC7 BITS 0xFFF8_2124 30 MDC30 22 MDC22 14 MDC14 6 MDC6 29 W Mask Disable Command Register 28 MDC28 20 MDC20 12 MDC12 4 MDC4 27 MDC27 19 MDC19 11 MDC11 3 MDC3 DESCRIPTIONS Undefined 25 MDC25 17 MDC17 9 MDC9 1 MDC1 24 MDC24 16 MDC16 8 MDC8 0 RESERVED 26 MDC26 18 MDC18 10 MDC10 2 MDC2 MDC29 21 MDC21 13 MDC13 5 MDC5 MDC x: Mask Disable Command [31:1] MDCx 0 = No effect 1 = Disables the corresponding interrupt channel [0] Reserved Reserved AIC Source Set Command Register (AIC_SSCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SSCR 31 SSC31 23 SSC23 15 SSC15 7 SSC7 0xFFF8_2128 30 SSC30 22 SSC22 14 SSC14 6 SSC6 29 W Source Set Command Register 28 SSC28 20 SSC20 12 SSC12 4 SSC4 27 SSC27 19 SSC19 11 SSC11 3 SSC3 26 SSC26 18 SSC18 10 SSC10 2 SSC2 25 SSC25 17 SSC17 9 SSC9 1 SSC1 Undefined 24 SSC24 16 SSC16 8 SSC8 0 RESERVED SSC29 21 SSC21 13 SSC13 5 SSC5 - 376 - W90P710 BITS DESCRIPTIONS [31:1] SSCx When the W90P710 is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SSCx: Source Set Command 0 = No effect. 1 = Activates the corresponding interrupt channel [0] Reserved Reserved AIC Source Clear Command Register (AIC_SCCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCCR 31 SCC31 23 SCC23 15 SCC15 7 SCC7 BITS 0xFFF8_212C 30 SCC30 22 SCC22 14 SCC14 6 SCC6 29 W Source Clear Command Register 28 SCC28 20 SCC20 12 SCC12 4 SCC4 27 SCC27 19 SCC19 11 SCC11 3 SCC3 DESCRIPTIONS Undefined 25 SCC25 17 SCC17 9 SCC9 1 SCC1 24 SCC24 16 SCC16 8 SCC8 0 RESERVED 26 SCC26 18 SCC18 10 SCC10 2 SCC2 SCC29 21 SCC21 13 SCC13 5 SCC5 [31:1] SCCx When the W90P710 is under debugging or verification, software can deactivate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SCCx: Source Clear Command 0 = No effect. 1 = Deactivates the corresponding interrupt channels [0] Reserved Reserved - 377 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 AIC End of Service Command Register (AIC_EOSCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_EOSCR 0xFFF8_2130 31 --23 --15 --7 --30 --22 --14 --6 --29 --21 --13 --5 --- W End of Service Command Register 28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 --25 --17 --9 --1 --- Undefined 24 --16 --8 --0 --- BITS DESCRIPTIONS [31:0] EOSCR This register is used by the interrupt service routine to indicate that it is completely served. Thus, the interrupt handler can write any value to this register to indicate the end of its interrupt service. AIC ICE/Debug Register (AIC_TEST) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_TEST 31 23 15 7 0xFFF8_2200 30 22 14 6 29 21 13 5 W ICE/Debug mode Register 28 20 12 4 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 Undefined 24 16 8 0 TEST RESERVED RESERVED RESERVED - 378 - W90P710 BITS DESCRIPTIONS [31:1] Reserved Reserved This register indicates whether AIC_IPER will be cleared or not after been read. If bit0 of AIC_TEST has been set, ICE or debug monitor can read AIC_IPER for verification and the AIC_IPER will not be cleared automatically. Write access to the AIC_IPER will perform the interrupt stacking in this mode. TEST: ICE/Debug mode 0 = normal mode. 1 = ICE/Debug mode. [0] TEST - 379 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.15 General-Purpose Input/Output The General-Purpose Input/Output (GPIO) module possesses 71 pins and serves multiple function purposes. Each port can be configured by software to meet various system configurations and design requirements. Software must configure each pin before starting the main program. If a pin is not used for multiplexed functions, the pin can be configured as I/O port Two extended interrupts nIRQ4 (GPIO0 pin) and nIRQ5 (nWAIT pin) are used the same interrupt request (channel #31) of AIC. It can be programmed as low/high sensitive or positive/negative edge triggered. When interrupt #31 assert in AIC, software can poll XISTATUS status register to identify which interrupt occur. These 71 IO pins are divided into 7 groups according to its peripheral interface definition. Port0: 5-pin input/output port Port1: 10-pin input/output port Port2: 10-pin input/output port Port3: 8-pin input/output port Port4: 11-pin input/output port Port5: 15-pin input/output port Port6: 12-pin input/output port Table 7.16.1 GPIO multiplexed functions table PORT0 0 1 2 3 4 PORT1 0 1 2 3 4 5 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 Configurable Pin Functions AC97_nRESET (I2S_MCLK) AC97_DATAI (I2S_DATAI) AC97_DATAO (I2S_DATAO) AC97_SYNC (I2S_LRCLK) AC97_BITCLK (I2S_BITCLK) SC1_PWR SC1_PRES SC1_RST SC1_CLK SC1_DAT SC0_PWR nIRQ4 PWM0 PWM1 PWM2 PWM3 USBPWREN DTR3 DSR3 TXD3 RXD3 Configuration Pin Functions nXDACK nXDREQ SD_CD SD_DAT3 SD_DAT2 VD8 VD9 VD10 VD11 VD12 VD13 - 380 - W90P710 Table 7.16.1 GPIO multiplexed functions table, continued 6 7 8 9 PORT2 0 1 2 3 4 5 6 7 8 9 PORT3 0 1 2 3 4 5 6 7 PORT4 0 1 2 3 4 5 6 GPIO26 GPIO27 GPIO28 GPIO29 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66 GPIO67 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 SC0_PRES SC0_RST SC0_CLK SC0_DAT PHY_RXERR PHY_CRSDV PHY_RXD[0] PHY_RXD[1] PHY_REFCLK PHY_TXEN PHY_TXD[0] PHY_TXD[1] PHY_MDIO PHY_MDC D24 D25 D26 D27 D28 D29 D30 D31 D16 D17 D18 D19 D20 D21 D22 SD_DAT1 SD_DAT0 SD_CLK SD_CMD VD14 VD15 VD16 VD17 - Configuration Pin Functions KPCOL0 KPCOL1 KPCOL2 KPCOL3 KPCOL4 KPCOL5 KPCOL6 KPCOL7 KPROW0 KPROW1 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 Configuration Pin Functions VD8 VD9 VD10 VD11 VD12 VD13 VD14 Configuration Pin Functions - 381 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Table 7.16.1 GPIO multiplexed functions table, continued 7 8 9 10 PORT5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PORT6 0 1 2 3 4 5 6 7 8 9 10 11 GPIO59 GPIO68 GPIO69 GPIO70 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GP1O17 GPIO18 GPIO19 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 D23 VD15 nWBE2/SDQM2 nWBE3/SDQM3 nWAIT nIRQ5 Configuration Pin Functions TXD0 RXD0 TXD1 RXD1 TXD2 CTS1 RXD2 RTS1 SCL0 SFRM SDA0 SSPTXD SCL1 SCLK SDA1 SSPRXD nWDOG USBPWREN nIRQ0 nIRQ1 USBOVRCUR nIRQ2 nIRQ3 Configuration Pin Function VCLK KPROW0 VDEN KPROW1 VSYNC KPROW2 HSYNC KPROW3 VD0 KPCOL0 VD1 KPCOL1 VD2 KPCOL2 VD3 KPCOL3 VD4 KPCOL4 VD5 KPCOL5 VD6 KPCOL6 VD7 KPCOL7 PS2CLK PS2DATA TIMER0 TIMER1 KPROW3 KPROW2 - - 382 - W90P710 7.15.1 GPIO Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG0 GPIO_DIR0 GPIO_DATAOUT0 GPIO_DATAIN0 GPIO_CFG1 GPIO_DIR1 GPIO_DATAOUT1 GPIO_DATAIN1 GPIO_CFG2 GPIO_DIR2 GPIO_DATAOUT2 GPIO_DATAIN2 GPIO_CFG3 GPIO_DIR3 GPIO_DATAOUT3 GPIO_DATAIN3 GPIO_CFG4 GPIO_DIR4 GPIO_DATAOUT4 GPIO_DATAIN4 0xFFF8_3000 0xFFF8_3004 0xFFF8_3008 0xFFF8_300C 0xFFF8_3010 0xFFF8_3014 0xFFF8_3018 0xFFF8_301C 0xFFF8_3020 0xFFF8_3024 0xFFF8_3028 0xFFF8_302C 0xFFF8_3030 0xFFF8_3034 0xFFF8_3038 0xFFF8_303C 0xFFF8_3040 0xFFF8_3044 0xFFF8_3048 0xFFF8_304C R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R GPIO port0 configuration register GPIO port0 direction control register GPIO port0 data output register GPIO port0 data input register GPIO port1 configuration register GPIO port1 direction control register GPIO port1 data output register GPIO port1 data input register GPIO port2 configuration register GPIO port2 direction control register GPIO port2 data output register GPIO port2 data input register GPIO port3 configuration register GPIO port3 direction control register GPIO port3 data output register GPIO port3 data input register GPIO port4 configuration register GPIO port4 direction control register GPIO port4 data output register GPIO port4 data input register 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_5555 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0015_5555 0x0000_0000 0x0000_0000 0xXXXX_XXXX - 383 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 GPIO Control Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG5 GPIO_DIR5 GPIO_DATAOUT5 GPIO_DATAIN5 GPIO_CFG6 GPIO_DIR6 GPIO_DATAOUT6 GPIO_DATAIN6 GPIO_DBNCECON GPIO_XICFG GPIO_XISTATUS 0xFFF8_3050 0xFFF8_3054 0xFFF8_3058 0xFFF8_305C 0xFFF8_3060 0xFFF8_3064 0xFFF8_3068 0xFFF8_306C 0xFFF8_3070 0xFFF8_3074 0xFFF8_3078 R/W R/W R/W R R/W R/W R/W R R/W R/W R/W GPIO port5 configuration register GPIO port5 direction control register GPIO port5 data output register GPIO port5 data input register GPIO port6 configuration register GPIO port6 direction control register GPIO port6 data output register GPIO port6 data input register GPIO input debounce control register Extend Interrupt Configure Register Extend Interrupt Status Register 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0xXXXX_XXX0 0xXXXX_XXX0 7.15.2 GPIO Register Description GPIO Port0 Configuration Register (GPIO_CFG0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG0 31 23 15 7 PT0CFG3 30 22 14 6 0xFFF8_3000 29 21 13 5 R/W 28 20 12 4 GPIO port0 configuration register 27 19 11 3 PT0CFG1 26 18 10 2 25 17 9 0x0000_0000 24 16 8 PT0CFG4 1 PT0CFG0 0 RESERVED RESERVED RESERVED PT0CFG2 - 384 - W90P710 11 Name USB_PWREN Type O 10 Name Type 01 Name AC97RESET PORT00 nIRQ4 or I2SMCLK 11 Name DTR3 Type O 10 Name PWM0 Type O 01 Name AC97DATAI PORT0_1 or I2SDATAI 11 Name DSR3 Type I 10 Name PWM1 Type O 01 Name AC97DATAO PORT0_2 or I2SDATAO 11 Name TXD3 Type O 10 Name PWM2 Type O 01 Name AC97SYNC PORT0_3 or I2SLRCLK 11 Name RXD3 Type O 10 Name PWM3 Type O 01 Name AC97BITCLK PORT0_4 or I2SBITCLK O Type I GPIO4 I/O 00 Name Type O GPIO3 I/O Type 00 Name Type O GPIO2 I/O Type 00 Name Type O GPIO1 I/O Type 00 Name Type O GPIO0 I/O Type 00 Name Type PT0CFG0 PT0CFG1 PT0CFG2 PT0CFG3 PT0CFG4 GPIO Port0 Direction Register (GPIO_DIR0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR0 0xFFF8_3004 R/W GPIO port0 in/out direction control and pull-up enable register 0x0000_0000 - 385 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 RESERVED 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 OMDEN0[4:0] 25 17 9 1 24 16 8 0 RESERVED RESERVED RESERVED PUPEN0[3:0] Bits [31:20] RESERVED - Description GPIO3 -GPIO0 port pin internal pull-up resister enable There are 4 bits for this register, the corresponding bit is set to "1" will enable pull-up resister on IO pin. 1 = enable [19:16] PUPEN0 0 = disable After power on the pull-up resisters are disabled. NOTE: GPIO4 is used as AC97 BITCLK input, an IO pad with Schmitt trigger input buffer PDB04SDGZ is implemented for this pin. Due to TSMC IO library without pull-up register, an external pull-up resister is necessary. [15:5] RESERVED GPIO4 ~GPIO0 output mode enable 1 = output mode 0 = input mode [4:0] OMDEN0 NOTE: Output mode enable bits are valid only when bit PT0CFG4-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port0 Data Output Register (GPIO_DATAOUT0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT0 0xFFF8_3008 R/W GPIO port0 data output register 0x0000_0000 - 386 - W90P710 31 23 15 7 30 22 14 6 RESERVED 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 DATAOUT0 25 17 9 1 24 16 8 0 RESERVED RESERVED RESERVED BITS DESCRIPTION [31:5] [4:0] RESERVED DATAOUT0 PORT0 data output value Writing data to this register will reflect the data value on the corresponding pin when it is configured as general output pin. And writing data to reserved bits is not effective. GPIO Port0 Data Input Register (GPIO_DATAIN0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN0 31 23 15 7 30 22 14 6 0xFFF8_300C 29 21 13 5 R/W 28 20 12 4 GPIO port0 data input register 27 19 11 3 26 18 10 2 DATAIN0 DESCRIPTION 0xXXXX_XXXX 25 17 9 1 24 16 8 0 RESERVED RESERVED RESERVED RESERVED BITS [31:5] [4:0] RESERVED DATAIN0 PORT0 data input value The DATAIN0 indicates the status of each GPIO0~GPIO4 port pin regardless of its operation mode. The reserved bits will be read as "0". - 387 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 GPIO Port1 Configuration Register (GPIO_CFG1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG1 31 23 15 PT1CFG7 7 PT1CFG3 6 30 22 14 0xFFF8_3010 29 21 13 R/W 28 20 12 GPIO port1 configuration register 27 19 PT1CFG9 11 PT1CFG5 3 PT1CFG1 10 2 9 26 18 25 17 0x0000_0000 24 16 PT1CFG8 8 PT1CFG4 1 PT1CFG0 0 RESERVED RESERVED PT1CFG6 5 PT1CFG2 4 *In the following pin definition, mark with shading is default function. PT1CFG0 PORT1_0 11 Name VD8 11 Name VD9 11 Name VD10 11 Name VD11 11 Name VD12 Type Type Type Type Type 10 Name SC1_PWR 10 Name SC1_PRES 10 Name SC1_RST 10 Name SC1_CLK 10 Name SC1_DAT Type O Type O Type O Type I Type O 01 Name nXDACK 01 Name nXDREQ 01 Name SD_CD 01 Name Type RESERVED 01 Name SD_DAT3 Type I/O Type I Type I Type O 00 Name GPIO20 00 Name GPIO21 00 Name GPIO22 00 Name GPIO23 00 Name GPIO24 Type I/O Type I/O Type I/O Type I/O Type I/O PT1CFG1 PORT1_1 PT1CFG2 PORT1_2 PT1CFG3 PORT1_3 PT1CFG4 PORT1_4 - 388 - W90P710 PT1CFG5 PORT1_5 11 Name VD13 11 Name VD14 11 Name VD15 11 Name VD16 11 Name VD17 Type Type Type Type Type 10 Name SC0_PWR 10 Name SC0_PRES 10 Name SC0_RST 10 Name SC0_CLK 10 Name SC0_DAT Type O Type O Type O Type O Type O 01 Name SD_DAT2 01 Name SD_DAT1 01 Name SD_DAT0 01 Name SD_CLK 01 Name SD_CMD Type I/O Type O Type I/O Type I/O Type I/O 00 Name GPIO25 00 Name GPIO26 00 Name GPIO27 00 Name GPIO28 00 Name GPIO29 Type I/O Type I/O Type I/O Type I/O Type I/O PT1CFG6 PORT1_6 PT1CFG7 PORT1_7 PT1CFG8 PORT1_8 PT1CFG9 PORT1_9 GPIO Port1 Direction Register (GPIO_DIR1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR1 0xFFF8_3014 R/W GPIO port0 in/out direction control and pull-up enable register 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 24 16 8 0 RESERVED PUPEN1[7:0] RESERVED OMDEN1[7:0] PUPEN1[9:8] OMDEN1[9:8] - 389 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:26] RESERVED GPIO51 ~ GPIO42 port pins internal pull-up resister enable This is a 10-bit registers, set corresponding bit to "1" will enable pull up resister in IO pin. 1 = enable 0 = disable After power on the resisters are disabled. PIO51 ~ GPIO42 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT1CFG9-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. [25:16] PUPEN1 [15:10] RESERVED [9:0] OMDEN1 GPIO Port1 Data Output Register (GPIO_DATAOUT1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT1 31 23 15 7 30 22 14 6 0xFFF8_3018 29 21 13 5 R/W 28 20 12 4 GPIO port1 data output register 27 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED 19 RESERVED 11 3 RESERVED DATAOUT1[7:0] BITS DESCRIPTION DATAOUT1[9:8] [31:10] RESERVED PORT1 data output value Writing data to this register will reflect the data value on the corresponding port1 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. [9:0] DATAOUT1 - 390 - W90P710 GPIO Port1 Data Input Register (GPIO_DATAIN1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN1 31 23 15 7 30 22 14 6 0xFFF8_301C 29 21 13 5 R/W 28 20 12 4 GPIO port1 data input register 27 RESERVED 19 RESERVED 11 3 10 2 9 1 18 17 26 25 0xXXXX_XXXX 24 16 8 0 RESERVED DATAIN1[7:0] BITS DESCRIPTION DATAIN1[9:8] [31:10] [9:0] RESERVED DATAIN1 Port1 input data register The DATAIN1 indicates the status of each GPIO29~GPIO20 pin regardless of its operation mode. The reserved bits are read as 0s. GPIO Port2 Configuration Register (GPIO_CFG2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG2 31 23 15 PT2CFG7 7 PT2CFG3 6 30 22 14 0xFFF8_3020 29 21 13 R/W 28 20 12 GPIO port2 configuration register 27 19 PT2CFG9 11 PT2CFG5 3 PT2CFG1 10 2 9 26 18 25 17 0x0000_0000 24 16 PT2CFG8 8 PT2CFG4 1 PT2CFG0 0 RESERVED RESERVED PT2CFG6 5 PT2CFG2 4 *In the following pin definition, mark with shading is default function. Publication Release Date: January 17, 2005 Revision A.2 - 391 - W90P710 11 Name LCD VD[8] 11 Name LCD VD[9] 11 Name LCD VD[10] 11 Name LCD VD[11] 11 Name LCD VD[12] 11 Name LCD VD[13] 11 Name LCD VD[14] 11 Name LCD VD[15] 11 Name LCD VD[16] Type O Type O Type O Type O Type O Type O Type O Type O Type O 10 Name KPCOL0 10 Name KPCOL1 10 Name KPCOL2 10 Name KPCOL3 10 Name KPCOL4 10 Name KPCOL5 10 Name KPCOL6 10 Name KPCOL7 10 Name KPROW0 Type O Type I Type I Type I Type I Type I Type I Type I Type I 01 Name PHY_RXERR 01 Name PHY_CRSDV 01 Name PHY_RXD[0] 01 Name PHY_RXD[1] 01 Name PHY_REFCLK 01 Name PHY_TXEN 01 Name PHY_TXD[0] 01 Name PHY_TXD[1] 01 Name PHY_MDIO Type I/O Type O Type O Type O Type I Type I Type I Type I Type I 00 Name GPIO42 00 Name GPIO43 00 Name GPIO44 00 Name GPIO45 00 Name GPIO46 00 Name GPIO47 00 Name GPIO48 00 Name GPIO49 00 Name GPIO50 Type I/O Type I/O Type I/O Type I/O Type I/O Type I/O Type I/O Type I/O Type I/O PT2CFG0 PORT2_0 PT2CFG1 PORT2_1 PT2CFG2 PORT2_2 PT2CFG3 PORT2_3 PT2CFG4 PORT2_4 PT2CFG5 PORT2_5 PT2CFG6 PORT2_6 PT2CFG7 PORT2_7 PT2CFG8 PORT2_8 - 392 - W90P710 11 Name LCD VD[17] Type O 10 Name KPROW1 Type O 01 Name PHY_MDC Type O 00 Name GPIO51 Type I/O PT2CFG9 PORT2_9 GPIO Port2 Direction Register (GPIO_DIR2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR2 0xFFF8_3024 R/W GPIO port2 in/out direction control and pull-up enable register 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 24 16 8 0 RESERVED PUPEN2[7:0] RESERVED OMDEN2[7:0] BITS DESCRIPTION PUPEN2[9:8] OMDEN2[9:8] [31:26] RESERVED GPIO51 ~ GPIO42 port pin internal pull-up resister enable This is a 10-bit register, write corresponding bit "1" will enable pull -up resister in the IO pin. 1 = enable 0 = disable After power on, the registers are disabled. GPIO51 ~ GPIO42 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT2CFG7-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. [25:16] PUPEN2 [15:10] RESERVED [9:0] OMDEN2 - 393 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 PGPIO Port2 Data Output Register (GPIO_DATAOUT2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT2 31 23 15 7 30 22 14 6 0xFFF8_3028 29 21 13 5 R/W 28 20 12 4 GPIO port2 data output register 27 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED 19 RESERVED 11 3 RESERVED DATAOUT2[7:0] BITS DESCRIPTION DATAOUT2[9:8] [31:10] RESERVED PORT2 data output value Writing data to this register will reflect the data value on the corresponding port2 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. [9:0] DATAOUT2 GPIO Port2 Data Input Register (GPIO_DATAIN2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN2 31 23 15 7 30 22 14 6 0xFFF8_302C 29 21 13 5 R/W 28 20 12 4 GPIO port2 data input register 27 19 11 3 26 18 10 2 25 17 9 1 0xXXXX_XXXX 24 16 8 0 RESERVED RESERVED RESERVED DATAIN2[7:0] DATAIN2[9:8] - 394 - W90P710 BITS DESCRIPTION [31:10] RESERVED Port2 input data register The DATAIN2 indicates the status of each GPIO42~GPIO51 pin regardless of its operation mode. The reserved bits will be read as 0s. [9:0] DATAIN2 GPIO Port3 Configuration Register (GPIO_CFG3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG3 31 23 15 PT3CFG7 7 PT3CFG3 6 30 22 14 0xFFF8_3030 29 21 13 R/W 28 20 12 GPIO port3 configuration register 27 19 11 PT3CFG5 3 PT3CFG1 26 18 10 2 25 17 9 0x0000_5555 24 16 8 PT3CFG4 1 PT3CFG0 0 RESERVED RESERVED PT3CFG6 5 PT3CFG2 4 *In the following pin definition, mark with shading is default function. PT3CFG0 PORT3_0 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 10 Name VD16 10 Name VD17 10 Name VD18 Type O D26 Type O D25 01 Name Type I/O Name GPIO62 Type O D24 01 Name Type I/O Name GPIO61 00 Type I/O 01 Name Type I/O Name GPIO60 00 Type I/O 00 Type I/O PT3CFG1 PORT3_1 PT3CFG2 PORT3_2 - 395 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 PT3CFG3 PORT3_3 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 10 Name VD19 10 Name VD20 10 Name VD21 10 Name VD22 10 Name VD23 Type O D31 Type O D30 Type O D29 Type O D28 Type O D27 01 Name Type I/O 01 Name Type I/O 01 Name Type I/O 01 Name Type I/O 01 Name Type I/O Name Name Name Name Name 00 Type I/O GPIO63 00 Type I/O GPIO64 00 Type I/O GPIO65 00 Type I/O GPIO66 00 Type I/O GPIO67 PT3CFG4 PORT3_4 PT3CFG5 PORT3_5 PT3CFG6 PORT3_6 PT3CFG7 PORT3_7 GPIO Port3 Direction Register (GPIO_DIR3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR3 0xFFF8_3034 R/W GPIO port3 in/out direction control and pull-up enable register 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 24 16 8 0 RESERVED PUPEN3[7:0] RESERVED OMDEN3[7:0] - 396 - W90P710 BITS DESCRIPTION [31:24] [23:16] RESERVED PUPEN2 After power on, the registers are disabled. GPIO67 ~ GPIO60 port pin internal pull-up resister enable 1 = enable 0 = disable After power on the pull-up registers are disabled GPIO67 ~ GPIO60 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT3CFG7-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. [15:8] RESERVED [7:0] OMDEN2 GPIO Port3 Data Output Register (GPIO_DATAOUT3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT3 31 23 15 7 30 22 14 6 0xFFF8_3038 29 21 13 5 R/W 28 20 12 4 GPIO port3 data output register 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED RESERVED RESERVED DATAOUT3[7:0] BITS DESCRIPTION [31:8] RESERVED PORT3 data output value Writing data to this register will reflect the data value on the corresponding port3 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. [7:0] DATAOUT3 - 397 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 GPIO Port3 Data Input Register (GPIO_DATAIN3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN3 31 23 15 7 30 22 14 6 0xFFF8_303C 29 21 13 5 R/W 28 20 12 4 GPIO port3 data input register 27 19 11 3 26 18 10 2 25 17 9 1 0xXXXX_XXXX 24 16 8 0 RESERVED RESERVED RESERVED DATAIN3[7:0] BITS DESCRIPTION [31:8] RESERVED Port3 input data register The DATAIN3 indicates the status of each GPIO67~GPIO60 pin regardless of its operation mode. The reserved bits will be read as 0s. [7:0] DATAIN3 GPIO Port4 Configuration Register (GPIO_CFG4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG4 31 23 15 PT4CFG7 7 PT4CFG3 6 30 22 14 0xFFF8_3040 29 21 13 R/W 28 20 12 GPIO port4 configuration register 27 19 PT4CFG9 11 PT4CFG5 4 3 PT4CFG1 2 1 10 9 26 18 25 17 0x0015_5555 24 16 PT4CFG8 8 PT4CFG4 0 PT4CFG0 RESERVED RESERVED PT4CFG10 PT4CFG6 5 PT4CFG2 - 398 - W90P710 *In the following pin definition, mark with shading is default function. PT4CFG0 PORT4_0 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED VD15 VD14 10 Name Type O D23 VD13 10 Name Type O D22 01 Name Type I/O Name GPIO59 VD12 10 Name Type O D21 01 Name Type I/O Name GPIO58 00 Type I/O VD11 10 Name Type O D20 01 Name Type I/O Name GPIO57 00 Type I/O VD10 10 Name Type O D19 01 Name Type I/O Name GPIO56 00 Type I/O VD9 10 Name Type O D18 01 Name Type I/O Name GPIO55 00 Type I/O VD8 10 Name Type O D17 01 Name Type I/O Name GPIO54 00 Type I/O 10 Name Type O D16 01 Name Type I/O Name GPIO53 00 Type I/O 01 Name Type I/O Name GPIO52 00 Type I/O 00 Type I/O PT4CFG1 PORT4_1 PT4CFG2 PORT4_2 PT4CFG3 PORT4_3 PT4CFG4 PORT4_4 PT4CFG5 PORT4_5 PT4CFG6 PORT4_6 PT4CFG7 PORT4_7 - 399 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 PT4CFG8 PORT4_8 11 Name Type RESERVED 11 Name Type RESERVED 11 Name Type RESERVED 10 Name Type RESERVED 10 Name Type RESERVED 10 Name nIRQ5 Type 01 Name nWBE2/SDQM2 01 Name nWBE3/SDQM3 01 Name nWAIT Type I Name Type I/O Name Type I/O Name 00 Type I/O GPIO68 00 Type I/O GPIO69 00 Type I/O GPIO70 PT4CFG9 PORT4_9 PT4CFG10 PORT4_10 GPIO Port4 Direction Register (GPIO_DIR4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR4 0xFFF8_3044 R/W GPIO port4 in/out direction control and pull-up enable register 27 19 11 3 26 18 10 2 25 0x0000_0000 31 23 15 7 30 22 14 6 29 RESERVED 21 13 RESERVED 5 28 20 12 4 24 16 8 0 PUPEN4[10:8] 17 9 OMDEN4[10:8] 1 OMDEN4[7:0] PUPEN4[7:0] BITS DESCRIPTION [31:27] [26:16] [15:11] RESERVED PUPEN4 RESERVED GPIO70~GPIO68 and GPIO59~GPIO52 pin internal pull-up resister enable 1 = enable 0 = disable - 400 - W90P710 Continued BITS DESCRIPTION GPIO70~GPIO68 and GPIO59~GPIO52 output mode enable 1 = enable 0 = disable [10:0] OMDEN4 NOTE: Output mode enable bits are valid only when bit PT4CFG10-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port4 Data Output Register (GPIO_DATAOUT4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT4 31 23 15 7 30 22 14 6 0xFFF8_3048 29 21 13 RESERVED 5 R/W 28 20 12 4 GPIO port4 data output register 27 19 11 3 26 18 10 2 25 17 9 0x0000_0000 24 16 8 0 RESERVED RESERVED DATAOUT4[10:8] 1 DATAOUT4[7:0] BITS DESCRIPTION [31:11] RESERVED PORT4 data output value Writing data to this register will reflect the data value on the corresponding port4 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. [10:0] DATAOUT4 GPIO Port4 Data Input Register (GPIO_DATAIN4) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN4 0xFFF8_304C R/W GPIO port4 data input register 0xXXXX_XXXX - 401 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 RESERVED 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 DATAIN4[10:8] 1 24 16 8 0 RESERVED RESERVED DATAIN3[7:0] BITS DESCRIPTION [31:11] RESERVED Port4 input data register The DATAIN4 indicates the status of each GPIO52~GPIO59, GPIO68 and GPIO69 pin regardless of its operation mode. The reserved bits will be read as 0s [10:0] DATAIN4 GPIO Port5 Configuration Register (GPIO_CFG5) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG5 31 23 15 PT5CFG7 7 PT5CFG3 6 30 22 14 0xFFF8_3050 29 21 13 R/W 28 20 12 GPIO port5 configuration register 27 19 PT5CFG9 11 PT5CFG5 3 PT5CFG1 10 2 9 26 18 25 17 0x0000_0000 24 16 PT5CFG8 8 PT5CFG4 1 PT5CFG0 0 RESERVED PT5CFG11 PT5CFG14 PT5CFG10 PT5CFG6 5 PT5CFG2 4 PT5CFG13 PT5CFG12 *In the following pin definition, mark with shading is default function. PT5CFG0 PORT5_0 11 Name Type Name FA20XL (USBH) 10 Type Name TXD0 RESERVED 01 Type O Name GPIO5 00 Type I/O - 402 - W90P710 11 Name Type Name IRQ1X (USBH) 11 Name Type Name IRQ12X (USBH) 11 Name Type Name T00X (USBH) 11 Name PS2CLK 11 Name PS2DATA 11 Name TIMER1 11 Name TIMER0 Type O Name SSPTX D 10 Type O Name SSPSCLK Type O Name SCL1 Type O Name SFRM 10 Type O Name SDA0 Type I/O Name RTS1 10 Type O Name SCL0 01 Type I/O Name GPIO12 Type O Name CTS1 10 Type IO Name RXD2 01 Type I/O Name GPIO11 00 Type I/O 10 Type Name RXD0 01 Type Name TXD1 01 Type Name RXD1 01 Type I Name TXD2 01 Type I Name GPIO10 00 Type I/O Type IO Name GPIO9 00 Type I/O Type I Name GPIO8 00 Type I/O Type O Name GPIO7 00 Type I/O RESERVED 10 RESERVED 10 RESERVED 10 01 Type I Name GPIO6 00 Type I/O 00 Type I/O PT5CFG1 PORT5_1 PT5CFG2 PORT5_2 PT5CFG3 PORT5_3 PT5CFG4 PORT5_4 PT5CFG5 PORT5_5 PT5CFG6 PORT5_6 PT5CFG7 PORT5_7 PT5CFG8 PORT5_8 11 Name KPROW2 01 Type I/O Name 00 Type I/O GPIO13 - 403 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 11 Name KPROW3 11 Name Type RESERVED 11 Name Type Name RESERVED 11 Name Type RESERVED 11 Name Type Name RESERVED 11 Name Type Name RESERVED Type O Name SSPRXD 10 Name USBPWREN 10 Type Name nIRQ0 01 Type I Name nIRQ1 01 Type Name nIRQ2 01 Type Name nIRQ3 Type I Name GPIO19 Type I Name GPIO18 00 Type I/O Type I Name GPIO17 00 Type I/O RESERVED 10 Name USBOVCUR 10 RESERVED 10 RESERVED Type O Name nWDOG 01 Type I Name GPIO16 00 Type I/O 10 Type I/O Name SDA1 01 Type O Name GPIO15 00 Type I/O 01 Type I/O Name GPIO14 00 Type I/O 00 Type I/O PT5CFG9 PORT5_9 PT5CFG10 PORT5_10 PT5CFG11 PORT5_11 PT5CFG12 PORT5_12 PT5CFG13 PORT5_13 PT5CFG14 PORT5_14 GPIO Port5 Direction Register (GPIO_DIR5) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR5 0xFFF8_3054 R/W GPIO port5 in/out direction control and pull-up enable register 0x0000_0000 - 404 - W90P710 31 RESERVED 23 15 RESERVED 7 30 22 14 6 29 21 13 5 28 20 PUPEN5[7:0] 12 4 27 PUPEN5[14:8] 19 11 OMDEN5[14:8] 3 26 18 10 2 25 17 9 1 24 16 8 0 OMDEN5[7:0] BITS DESCRIPTION [31] [30:16] [15] RESERVED PUPEN5 RESERVED GPIO19 ~ GPIO5 port pin internal pull-up resister enable 1 = enable 0 = disable GPIO19 ~ GPIO5 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT5CFG9-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. [14:0] OUTEN5 GPIO Port5 Data Output Register (GPIO_DATAOUT5) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT5 31 23 15 RESERVED 7 6 30 22 14 0xFFF8_3058 29 21 13 5 R/W 28 GPIO port5 data output register 27 19 11 DATAOUT5[14:8] 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED 20 RESERVED 12 4 DATAOUT5[7:0] - 405 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:15] RESERVED PORT5 data output value Writing data to this register will reflect the data value on the corresponding port5 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. [14:0] DATAOUT5 GPIO Port5 Data Input Register (GPIO_DATAIN5) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN5 31 23 15 RESERVED 7 6 30 22 14 0xFFF8_305C 29 21 13 5 R/W 28 GPIO port4 data input register 27 19 11 DATAIN5[14:8] 4 3 2 1 26 18 10 0xXXXX_XXXX 25 17 9 24 16 8 0 RESERVED 20 RESERVED 12 DATAIN5[7:0] BITS DESCRIPTION [31:15] RESERVED Port5 input data register The DATAIN5 indicates the status of each GPIO19~GPIO5 pin regardless of its operation mode. The reserved bits will be read as 0s. [14:0] DATAIN5 GPIO Port6 Configuration Register (GPIO_CFG6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG6 0xFFF8_3060 R/W GPIO port6 configuration register 0x0000_0000 - 406 - W90P710 31 23 15 PT6CFG7 7 PT6CFG3 30 22 14 6 29 21 13 PT6CFG6 5 PT6CFG2 28 20 12 4 27 19 PT6CFG9 11 PT6CFG5 3 PT6CFG1 26 18 10 2 25 17 PT6CFG8 9 PT6CFG4 1 PT6CFG0 24 16 8 0 RESERVED PT6CFG11 PT6CFG10 *In the following pin definition, mark with shading is default function. 11 Name Type Name KPROW0 10 Type Name KPROW1 10 Type Name KPROW2 10 Type Name KPROW3 10 Type Name KPCOL0 Type I Name VD0 Type O Name HSYNC 01 Type O Name GPIO34 Type O Name VSYNC 01 Type O Name GPIO33 00 Type I/O Type O Name VDEN 01 Type O Name GPIO32 00 Type I/O RESERVED 11 Name RESERVED 11 Name RESERVED 11 Name RESERVED 11 Name RESERVED 10 Type O Name VCLK 01 Type O Name GPIO31 00 Type I/O 01 Type O Name GPIO30 00 Type I/O 00 Type I/O PT6CFG0 PORT6_0 PT6CFG1 PORT6_1 PT6CFG2 PORT6_2 PT6CFG3 PORT6_3 PT6CFG4 PORT6_4 - 407 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 PT6CFG5 PORT6_5 11 Name Type Name RESERVED 11 Name Type Name RESERVED 11 Name Type Name RESERVED 11 Name Type Name RESERVED 11 Name Type Name RESERVED 11 Name Type Name RESERVED 11 Name Type Name RESERVED 10 Type I Name VD1 KPCOL1 10 Type I Name VD2 KPCOL2 10 Type I Name VD3 KPCOL3 10 Type I Name VD4 KPCOL4 10 Type I Name VD5 KPCOL5 10 Type I Name VD6 KPCOL6 10 Type I Name VD7 KPCOL7 01 Type O 01 Type O 01 Type O 01 Type O 01 Type O 01 Type O 01 Type O Name Name Name Name Name Name Name 00 Type I/O GPIO35 00 Type I/O GPIO36 00 Type I/O GPIO37 00 Type I/O GPIO38 00 Type I/O GPIO39 00 Type I/O GPIO40 00 Type I/O GPIO41 PT6CFG6 PORT6_6 PT6CFG7 PORT6_7 PT6CFG8 PORT6_8 PT6CFG9 PORT6_9 PT6CFG10 PORT6_10 PT6CFG11 PORT6_11 GPIO Port6 Direction Register (GPIO_DIR6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DIR6 0xFFF8_3064 R/W GPIO port5 in/out direction control and pull-up enable register 0x0000_0000 - 408 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 RESERVED PUPEN6[7:0] RESERVED OMDEN6[7:0] BITS DESCRIPTION PUPEN6[11:8] OMDEN6[11:8] [31:27] [26:16] [15:13] RESERVED PUPEN6 RESERVED GPIO30 ~GPIO41 port pin internal pull-up resister enable 1 = enable 0 = disable GPIO41 ~ GPIO30 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT6CFG11-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. [12:0] OMDEN6 GPIO Port6 Data Output Register (GPIO_DATAOUT6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAOUT6 31 23 15 7 30 22 14 6 0xFFF8_3068 29 21 13 5 R/W 28 20 12 4 GPIO port6 data output register 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED RESERVED RESERVED DATAOUT6[7:0] DATAOUT6[11:8] - 409 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:12] RESERVED PORT6 data output value Writing data to this register will reflect the data value on the corresponding port6 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective [11:0] DATAOUT6 GPIO Port6 Data Input Register (GPIO_DATAIN6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DATAIN6 31 23 15 7 30 22 14 6 0xFFF8_306C 29 21 13 5 R/W 28 20 12 4 GPIO port6 data input register 27 19 11 3 26 18 10 2 25 17 9 1 0xXXXX_XXXX 24 16 8 0 RESERVED RESERVED RESERVED DATAIN6[7:0] BITS DESCRIPTION DATAIN6[11:8] [31:12] [11:0] RESERVED DATAIN6 Port6 input data register The DATAIN6 indicates the status of each GPIO18~GPIO5 pin regardless of its operation mode. The reserved bits will be read as 0s. GPIO Debounce Control Register (GPIO_DBNCECON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_DBNCECON 0xFFF8_3070 R/W GPIO debounce control register 0xXXXX_XX00 - 410 - W90P710 31 23 15 7 RESERVED BITS 30 22 14 6 29 21 13 5 DBCLKSEL 28 20 12 4 27 RESERVED 19 RESERVED 11 RESERVED 3 DBEN3 DESCRIPTION 26 18 10 2 DBEN2 25 17 9 1 DBEN1 24 16 8 0 DBEN0 [31:7] RESERVED Debounce Clock Selection These 3 bits are used to select the clock rate for de-bouncer circuit. The relationship between the system clock HCLK and the de-bounce clock TCLK_BUN is as follows: TCLK_BUN = HCLK / 2DBCLKSEL Debounce circuit enable for GPIO19 (nIRQ3) 1 = enable 0 = disable Debounce circuit enable for GPIO18 (nIRQ2) [6:4] DBCLKSEL [3] DBEN3 [2] DBEN2 1 = enable 0 = disable Debounce circuit enable for GPIO17 (nIRQ1) [1] DBEN1 1 = enable 0 = disable Debounce circuit enable for GPIO16 (nIRQ0) [0] DBEN0 1 = enable 0 = disable GPIO Interrupt Configuration Register (GPIO_XICFG) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_XICFG 0xFFF8_3074 R/W Extend Register Interrupt Configure 0xXXXX_XX00 - 411 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 EnINT5 BITS 30 22 14 6 DBE5 29 21 13 5 ISTYPE5 28 20 12 4 27 19 11 3 EnINT4 DESCRIPTION 26 18 10 2 DBE4 25 17 9 1 ISTYPE4 24 16 8 0 RESERVED RESERVED RESERVED [31:8] RESERVED Enable INT5 Setting this bit 1 to enable extend interrupt 5. 1 = Enable interrupt 5 [7] EnINT5 0 = Disable interrupt 5 The AIC interrupt channel 31 is reserved for interrupt 5 and 4 (wired-OR), if this bit is set and interrupt 5 occur, then it will send an interrupt request signal into AIC module. Debounce circuit enable for INT5 (alternative function of nWAIT pin) Extend interrupt 5 shares the same debounce circuit with nIRQ[3:0], software can configure debounce sampling time in GPIO_DEBNCE control register. DBE5 function is the same as DBE0 in GPIO_DBENCE register. 1 = Enable debounce 0 = Disable debounce Interrupt 5 source type ISTYPE5 Interrupt Source Type LOW level sensitive HIGH level sensitive Negative edge triggered Positive edge triggered [6] DBE5 [5:4] STYPE5 2'b00 2'b01 2'b10 2'b11 - 412 - W90P710 Continued BITS DESCRIPTION [3] EnINT4 Enable INT4 Setting this bit 1 to enable extend interrupt 4 1 = Enable interrupt 4 0 = Disable interrupt 4 The AIC interrupt channel 31 is reserved for interrupt 5 and 4 (wire-OR), if this bit is set and interrupt 4 occur, then it will send an interrupt request signal into AIC module. Debounce circuit enable for INT4 (alternative function of GPIO0 pin) 1 = Enable debounce 0 = Disable debounce Extend interrupt 4 shares the same debounce circuit with nIRQ[3:0], software can configure debounce sampling time in GPIO_DEBNCE control register. DBE5 function is the same as DBE0 in GPIO_DBENCE register. Interrupt 4 source type ISTYPE5 2'b00 2'b01 2'b10 2'b11 Interrupt Source Type LOW level sensitive HIGH level sensitive Negative edge triggered Positive edge triggered [2] DBE4 [1:0] ISTYPE4 GPIO Interrupt Status Register (GPIO_XISTATUS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_XISTATUS 0xFFF8_3078 R/W Extend interrupt status (flag) register 27 19 11 3 26 18 10 2 25 17 9 1 INT5 0xXXXX_XX00 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 24 16 8 0 INT4 RESERVED RESERVED RESERVED RESERVED - 413 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTION [31:2] RESERVED Interrupt 5 status When interrupt input is detected with ISTYPE5 triggered condition, this flag will be set. It must be cleared by software. 1 = interrupt detected. 0 = No interrupt Interrupt 4 status When interrupt input is detected with ISTYPE4 triggered condition, this flag will be set. It must be cleared by software. 1 = interrupt 4 is detected. 0 = no interrupt [1] INT5 [0] INT4 - 414 - W90P710 7.16 Real Time Clock Real Time Clock (RTC) block can be operated by independent power supply while the system power is off. The RTC block utilizes an external crystal to generate 32.768 KHz clock. The RTC can transmit data to CPU as BCD values. The data include the time by second, minute, hour and the date by day, month, and year. In addition, to reach better frequency accuracy, the RTC counter can be adjusted by software. RTC features are shown as below: Time counter (second, minute, hour) and calendar counter (day, month, year). Alarm register (second, minute, hour, day, month, year). 12/24 hour mode selectable. Recognize leap year automatically. Day of the week counter. Frequency compensate register (RTC_FCR). Beside RTC_FCR, all clock and alarm data expressed in BCD code. Support tick time interrupt RTC Initiation: When RTC block is power on, programmer has to write a number (0xa5eb1357) to RTC_INIR to reset all logic. RTC_INIR act as hardware reset circuit. Once RTC_INIR has been set as 0xa5eb1357, user cannot reload any other value. RTC write enable: Register RTC_AER bit 15~0 is RTC read /write password. It is used to avoid signal interference from system during system power off. RTC_AER bit 15~0 has to be set as 0xa965 before user want to write new data into all registers besides RTC_INIR. If user set RTC_AER as 0xa965, RTC_WRITE_EN will be raised high. Then user can feel free to write data into register. RTC_WRITE_EN will keep high for a short period (about 24ms) and it will be pull low by internal state machine automatically. Frequency Compensation: The RTC_FCR allows software control digital compensation of a 32.768 KHz crystal oscillator. User can utilize a frequency counter to measure RTC clock in one of GPIO pin during manufacture, and store the value in Flash memory for retrieval when the product is first power on. Time and Calendar counter: RTC_TLR and RTC_CLR are used to load the time and calendar. RTC_TAR and RTC_CAR are used as alarm. They are all BCD counters. 12/24 hour Time scale selection: The 12/24 hour time scale selection depend on RTC_TSSR bit 0. Day of the week counter: Count from Sunday to Saturday - 415 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Tick Time interrupt: RTC block use a counter to calibrate the tick time count value. When the value in counter reaches zero, RTC will issue an interrupt. RTC register property: When system power is off but RTC power is on, data stored in RTC registers will not be lost except RTC_TSSR, RTC_RIER and RTC_RIIR. Because of difference between RTC clock and system clock, every time user write new data to any one register, the register will be updated until 2 RTC clock later (60us). In addition, user must be aware that RTC block does not check whether loaded data is out of bounds. RTC does not check rationality between RTC_DWR and RTC_CLR either. - 416 - W90P710 7.16.1 RTC Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_INIR RTC_AER RTC_FCR RTC_TLR RTC_CLR RTC_TSSR RTC_DWR RTC_TAR RTC_CAR RTC_LIR RTC_RIER RTC_RIIR RTC_TTR 0xFFF8_4000 0xFFF8_4004 0xFFF8_4008 0xFFF8_400C 0xFFF8_4010 0xFFF8_4014 0xFFF8_4018 0xFFF8_401C 0xFFF8_4020 0xFFF8_4024 0xFFF8_4028 0xFFF8_402C 0xFFF8_4030 R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/C R/W RTC Initiation Register RTC Access Enable Register RTC Frequency Register Compensation 0x0000_0000 0x0000_0700 0x0000_0000 0x0005_0101 0x0000_0001 0x0000_0006 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Time Loading Register Calendar Loading Register Time Scale Selection Register Day of the Week Register Time Alarm Register Calendar Alarm Register Leap year Indicator Register RTC Interrupt Enable Register RTC Interrupt Indicator Register RTC Tick Time Register RTC Initiation Register (RTC_INIR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_INIR 31 23 15 7 0xFFF8_4000 R/W RTC Initiation Register 30 22 14 6 29 21 13 5 28 20 12 4 INIR[7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 INIR[31:24] INIR[23:16] INIR[15:8] - 417 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS INIR [31:0]: [31:0] INIR The INIR register is used to replace hardware reset circuit. User must write INIR as "0xa5eb_1357" after RTC is power on. INIR [0]: R/W. Once RTC INIR has been written, user can access this bit to find out whether RTC reset signal is pulled high. RTC Access Enable Register (RTC_AER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_AER 0xFFF8_4004 R/W RTC Access Enable Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 AER[7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 AER[16] 8 0 AER[15:8] BITS DESCRIPTIONS [31:17] Reserved AER [16]: Read only 1 = RTC register write enable 0 = RTC register write disable [16:0] AER AER[15:0]: Write only RTC register write enable/disable password 0xa965 = write enable 0x0000 = write disable - 418 - W90P710 RTC Frequency Compensation Register (RTC_FCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_FCR 0xFFF8_4008 R/W RTC Frequency Compensation Register 0X0000_0700 31 23 15 7 Reserved 30 22 14 Reserved 6 29 21 13 5 28 Reserved 20 Reserved 12 4 27 19 11 3 FCR_fra 26 18 10 FCR_int 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:12] Reserved FCR [11:8]: Integer part Integer part of detected value 32776 32775 32774 32773 32772 32771 32770 32769 Fraction part FCR[11:8] Integer part of detected value 32768 32767 32766 32765 32764 32763 32762 32761 FCR[11:8] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 [11:8] FCR_int [5:0] FCR_fra Formula: FCR_int = (fraction part of detected value) X 60 Note: Digit in FCR must be expressed as hexadecimal number. - 419 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS Frequency counter measurement: 32773.65Hz Example 1 FCR Calibration Example 2 Integer part: 32773 => FCR [11:8] = 0xc Fraction part: 0.65 X 60 = 39(0x27) => FCR[5:0]=0x27 Frequency counter measurement: 32765.27Hz Integer part: 32765=> FCR [11:8] = 0x4 Fraction part: 0.27 X 60 = 16.2(0x10) => FCR [5:0] = 0x10 RTC Time Loading Register (RTC_TLR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TLR 0xFFF8_400C R/W RTC Time Loading Register 0X0000_0000 31 23 Reserved 15 Reserved 7 Reserved 30 22 29 21 Hi_hr 28 Reserved 20 27 19 26 18 Lo_hr 25 17 24 16 14 13 Hi_min 12 11 10 Lo_min 9 8 6 5 Hi_sec 4 3 2 Lo_sec 1 0 Note: TLR is a BCD digit counter and RTC will not check loaded data. BITS DESCRIPTIONS [21:20] [19:16] [14:12] [11:8] [6:4] [3:0] Hi_hr Lo_hr Hi_min Lo_min Hi_sec Lo_sec 10 hour time digit 1 hour time digit 10 min time digit 1 min time digit 10 sec time digit 1 sec time digit - 420 - W90P710 RTC Calendar Loading Register (RTC_CLR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_CLR 0xFFF8_4010 R/W RTC Calendar Loading Register 0X0005_0101 31 23 15 7 Reserved 30 22 Hi_year 14 Reserved 6 29 21 13 5 Hi_day 28 Reserved 20 12 Hi_mon 4 27 19 11 3 26 18 Lo_year 10 Lo_mon 2 Lo_day 25 17 9 1 24 16 8 0 Note: CLR is a BCD digit counter and RTC will not check loaded data. BITS DESCRIPTIONS [23:20] [19:16] [12] [11:8] [5:4] [3:0] Hi_year Lo_year Hi_mon Lo_mon Hi_day Lo_day 10-year calendar digit 1-year calendar digit 10-month calendar digit 1-month calendar digit 10-day calendar digit 1-day calendar digit RTC Time Scale Selection Register (RTC_TSSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TSSR 0xFFF8_40014 R/W Time Scale Selection Register 0X0000_0001 - 421 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 24Hr/12Hr BITS DESCRIPTIONS [31:1] Reserved 24Hr/12Hr : 24hour / 12 hour mode selection It indicate that TLR and TAR are in 24-hour mode or 12-hour mode 1 = select 24-hour time scale 0 = select 12-hour time scale with am and pm indication 24-hour time scale 12-hour time scale 24-hour time scale 12-hour time scale 00 01 [0] 24Hr/12Hr 02 03 04 05 06 07 08 09 10 11 12(AM12) 01(AM01) 02(AM02) 03(AM03) 04(AM04) 05(AM05) 06(AM06) 07(AM07) 08(AM08) 09(AM09) 10(AM10) 11(AM11) 12 13 14 15 16 17 18 19 20 21 22 23 32(PM12) 21(PM01) 22(PM02) 23(PM03) 24(PM04) 25(PM05) 26(PM06) 27(PM07) 28(PM08) 29(PM09) 30(PM10) 31(PM11) - 422 - W90P710 RTC Day of the Week Register (RTC_DWR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_DWR 0xFFF8_4018 R/W Day of the Week Register 0X0000_0006 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 DWR[2:0] 24 16 8 0 BITS DESCRIPTIONS [31:3] Reserved DWR[2:0] : Day of the Week Register 0 1 Sunday Monday Tuesday Wednesday Thursday Friday Saturday [2:0] DWR 2 3 4 5 6 RTC Time Alarm Register (RTC_TAR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TAR 0xFFF8_401C R/W RTC Time Alarm Register 0X0000_0000 - 423 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 Reserved 15 Reserved 7 Reserved 30 22 14 6 29 21 13 Hi_min_alarm 5 Hi_sec_alarm 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Hi_hr_alarm Hi_hr_alarm Lo_min_alarm Lo_sec_alarm TAR is a BCD digit register and RTC will not check loaded data. BITS DESCRIPTIONS [31:22] [21:20] [19:16] [15] [14:12] [11:8] [7] [6:4] [3:0] Reserved Hi_hr_alarm Lo_hr_alarm Reserved Hi_min_alarm Lo_min_alarm Reserved Hi_sec_alarm Lo_sec_alarm 10 hour time digit 1 hour time digit 10 min time digit 1 min time digit 10 sec time digit 1 sec time digit RTC Calendar Alarm Register (RTC_CAR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_CAR 0xFFF8_4020 R/W RTC Calendar Alarm Register 0X0000_0000 - 424 - W90P710 31 23 15 30 22 14 Reserved 29 21 13 28 Reserved 20 12 Hi_mon_ alarm 27 19 11 26 18 10 25 17 9 24 16 8 Hi_year_alarm Lo_year_alarm Lo_mon_alarm 3 2 1 0 7 Reserved 6 5 4 Hi_day_alarm Lo_day_alarm CAR is a BCD digit register and RTC will not check loaded data. BITS DESCRIPTIONS [31:24] [23:20] [19:16] [15:13] [12] [11:8] [5:4] [3:0] Reserved Hi_year Lo_year Reserved Hi_mon Lo_mon Hi_day Lo_day 10-year calendar digit 1-year calendar digit 10-month calendar digit 1-month calendar digit 10-day calendar digit 1-day calendar digit RTC Leap year Indication Register (RTC_LIR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_LIR 0xFFF8_4024 R RTC Leap year Indication Register 0X0000_0000 - 425 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 LIR[0] BITS DESCRIPTIONS [31:1] Reserved LIR [0]: Real only. Leap year Indication REGISTER [0] LIR 1 = It indicate that this year is leap year 0 = It indicate that this year is not a leap year RTC Interrupt Enable Register (RTC_RIER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_RIER 0xFFF8_4028 R/W RTC Interrupt Enable Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 Tick_int_en 24 16 8 0 Alarm_int_en - 426 - W90P710 BITS DESCRIPTIONS [31:2] [1] Reserved Tick_int_en Alarm_int_e n 1 = RTC Time Tick Interrupt and counter enable 0 = RTC Time Tick Interrupt and counter disable 1 = RTC Alarm Interrupt enable 0 = RTC Alarm Interrupt disable [0] RTC Interrupt Indication Register (RTC_RIIR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_RIIR 0xFFF8_402C R/C RTC Interrupt Indication Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 Tick_int_st 24 16 8 0 Alarm_int_st BITS DESCRIPTIONS [31:2] Reserved RTC Time Tick Interrupt Indication REGISTER 1 = It indicates that time tick interrupt has been activated. [1] Tick_int_st 0 = It indicates that time tick interrupt has never occurred. Software Can also clear this bit after RTC interrupt has occur. - 427 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS RTC Alarm Interrupt Indication REGISTER 1 = It indicates that time counter and calendar counter have counted [0] Alarm_int_st to a specified time recorded in TAR and CAR. RTC alarm interrupt has been activated. 0 = It indicates that alarm interrupt has never occurred. Software can Also clear this bit after RTC interrupt has occurred. Note : User can clear these two bits by writing 0x0 to RIIR RTC Tick Time Register (RTC_TTR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TTR 0xFFF8_4030 R/W RTC Tick Time Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 TTI 24 16 8 0 - 428 - W90P710 BITS DESCRIPTIONS [31:3] Reserved RTC Tick Time Interrupt request Interval The TTR [2:0] is used to select tick time interrupt request interval. The period of tick time interrupt is as follow: TTR[2:0] 0 1 2 3 4 5 6 7 Tick Time interrupt interval 1 sec 1/2 sec 1/4 sec 1/8 sec 1/16 sec 1/32 sec 1/64 sec 1/128 sec [2:0] TTI - 429 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.17 Smart Card Host Interface The Smart Card resides in APB bus. The whole chip of W90P710 operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode. ISO-7816 compliant PC/SC T=0, T=1 compliant 16-byte transmitter FIFO and 16-byte receiver FIFO FIFO threshold interrupt to optimize system performance Programmable transmission clock frequency Versatile baud rate configuration UART-like register file structure Versatile 8-bit, 16-bit, 24-bit time-out counter for Answer-To-Reset (ATR) and waiting times processing. Parity error counter in reception mode and in transmission mode with automatic re-transmission. Automatic activation and deactivation sequence through an independence sequencer 7.17.1 Register Mapping R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written. Table 7.12.2.1 Smart Card Host Interface 0 Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE Smartcard Host Interface 0 SCHI_RBR0 SCHI_TBR0 SCHI_IER0 SCHI_ISR0 SCHI_SCFR0 SCHI_SCCR0 SCHI_CBR0 SCHI_SCSR0 SCHI_GTR0 SCHI_ECR0 SCHI_TMR0 SCHI_TOC0 0xFFF8_5000 (BDLAB=0) R Receiver Buffer Register Undefined Undefined 0x0000_0080 0X0000_00C1 0x0000_0000 0x0000_0018 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF8_5000 (BDLAB=0) W Transmitter Buffer Register 0xFFF8_5004 (BDLAB=0) R/W Interrupt Enable Register 0xFFF8_5008 (BDLAB=0) 0xFFF8_500C 0xFFF8_5010 0xFFF8_5014 0xFFF8_5018 0xFFF8_501C 0xFFF8_5020 0xFFF8_5028 R Interrupt Status Register 0xFFF8_5008 (BDLAB=0) W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 SCHI_TOIR0_0 0xFFF8_502C - 430 - W90P710 Table 7.12.2.1 Smart Card Host Interface 0 Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR1_0 0xFFF8_5030 SCHI_TOIR2_0 0xFFF8_5034 SCHI_TOD0_0 0xFFF8_5038 SCHI_TOD1_0 0xFFF8_503C SCHI_TOD2_0 0xFFF8_5040 SCHI_BTOR_0 0xFFF8_5044 SCHI_BLL_0 SCHI_BLH_0 SCHI_ID_0 SCHI_RBR1 SCHI_TBR1 SCHI_IER1 SCHI_ISR1 SCHI_SCFR1 SCHI_SCCR1 SCHI_CBR1 SCHI_SCSR1 SCHI_GTR1 SCHI_ECR1 SCHI_TMR1 SCHI_TOC1 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 R/W Buffer Time out Data Register 0xFFF8_5000 (BDLAB=1) R/W 0xFFF8_5004 (BDLAB=1) R/W 0xFFF8_5008 (BDLAB=1) 0xFFF8_5800 (BDLAB=0) R R Baud Rate Divisor Latch Lower Byte 0x0000_001F Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register Receiver Buffer Register 0x0000_0070 Undefined Undefined 0x0000_0080 0X0000_00C1 0x0000_0000 0x0000_0018 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 Smartcard Host Interface 1 0xFFF8_5800 (BDLAB=0) W Transmitter Buffer Register 0xFFF8_5804 (BDLAB=0) R/W Interrupt Enable Register 0xFFF8_5808 (BDLAB=0) 0xFFF8_580C 0xFFF8_5810 0xFFF8_5814 0xFFF8_5818 0xFFF8_581C 0xFFF8_5820 0xFFF8_5828 R Interrupt Status Register 0xFFF8_5808 (BDLAB=0) W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 SCHI_TOIR0_1 0xFFF8_582C SCHI_TOIR1_1 0xFFF8_5830 SCHI_TOIR2_1 0xFFF8_5834 SCHI_TOD0_1 0xFFF8_5838 SCHI_TOD1_1 0xFFF8_583C SCHI_TOD2_1 0xFFF8_5840 SCHI_BTOR1 SCHI_BLL1 SCHI_BLH1 SCHI_ID1 0xFFF8_5844 R/W Buffer Time out Data Register 0xFFF8_5800 (BDLAB=1) R/W 0xFFF8_5804 (BDLAB=1) R/W 0xFFF8_5808 (BDLAB=1) R Baud Rate Divisor Latch Lower Byte 0x0000_001F Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register 0x0000_0070 - 431 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.17.2 Register Description Receive Buffer Register (SCHI_RBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_RBR0 SCHI_RBR1 31 23 15 7 0XFFF8_5000 (DLAB = 0) 0xFFF8_5800 (DLAB = 0) 30 22 14 6 29 21 13 5 R R Receiver Buffer Register 0 Receiver Buffer Register 1 26 18 10 2 25 17 9 1 Undefined Undefined 24 16 8 0 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 RxBDATA[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8-bit Received Data [7:0] RxBDATA By reading this register, the SCHI will return an 8-bit data received from SCx_DAT pin. This register is the access port for receiver FIFO. The depth of receiver FIFO is 16 bytes. Transmit Buffer Register (SCHI_TBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TBR0 SCHI_TBR1 0xFFF8_5000(DLAB = 0) 0xFFF8_5800(DLAB = 0) W W Transmit Buffer Register 0 Transmit Buffer Register 1 Undefined Undefined - 432 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 TxBDATA[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8-bit Transmit Buffer Data [7:0] TxBDATA By writing to this register, the SCHI will send out an 8-bit data through the SCx_DAT pin. This register is the access port for transmitter FIFO. transmitter FIFO is 16 bytes. The depth of Interrupt Enable register (SCHI_IER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_IER0 SCHI_IER1 0xFFF8_5004 (DLAB = 0) 0xFFF8_5804 (DLAB = 0) R/W Interrupt Enable Register 0 R/W Interrupt Enable Register 1 0x0000_0080 0x0000_0080 31 23 15 7 PWRDN 30 22 14 6 Interface 29 21 13 RESERVED 28 20 12 4 27 19 11 3 ESCPTI 26 18 10 ETOR2 2 ESCSRI 25 17 9 ETOR1 1 ETBREI 24 16 8 ETOR0 0 ERDRI RESERVED RESERVED 5 RESERVED - 433 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:11] RESERVED TOR2 interrupt enable bit When 24 bit time-out counter decrease to zero, it will set TO2 flag to high. If we set ETOR2 to high, then the 24 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. TOR1 interrupt enable bit When 16 bit time-out counter decrease to zero, it will set TO1 flag to high. If we set ETOR1 to high, then the 16 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. TOR0 interrupt enable bit When 8 bit time-out counter decrease to zero, it will set TO0 flag to high. If we set ETOR0 to high, then the 8 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. Smart card POWER DOWN bit PWRDN is used when the Smartcard controller needs to be powered down. Powering down must be done whenever the controller needs to switch between class A and B. When this bit is a `1', it will deactivate all contacts to the Smartcard except for SCRST_L which will be discussed later. Smart card different interface bit Interface is used for controlling the different power control device signals. When `1', the controller will direct a power control pin is active high. When `0', a power control pin is active low to meet different power control interface. Reserved for future Smart card present toggle interrupt enable bit A rising/falling edge of SCPSNT signal triggers an interrupt if this bit is set to "1". 0 = SCPSNT toggle interrupt is disabled. 1 = SCPSNT toggle interrupt is enabled. Enable SCSR interrupt bit An ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error, no stop bit error, parity bit error or overrun error. Any SCSR-related event as described above will trigger an interrupt if this bit is set to "1". 0 = SCSR-related event interrupt is disabled. 1 = SCSR-related event interrupt is enabled. [10] ETOR2 [9] ETOR1 [8] ETOR0 [7] PWRDN [6] Interface [5:4] RESERVED [3] ESCPTI [2] ESCSRI - 434 - W90P710 Continued BITS DESCRIPTIONS Enable Transmit Buffer Empty interrupt bit [1] ETBREI An ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An interrupt is issued when TBR is empty and this bit is set to "1". 0 = TBR empty interrupt is disabled. 1 = TBR empty interrupt is enabled. Enable Receive Data Ready interrupt bit The active FIFO threshold level for this kind of interrupt when FIFO is enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of SCFR at base address + 8. Refer to description of SCFR for details). An interrupt is issued if a data byte is ready for host to read when FIFO is disabled or incoming data from card reaches active FIFO threshold level when FIFO is enabled. [0] ERDRI Interrupt Status Register (SCHI_ISR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_ISR0 SCHI_ISR1 0xFFF8_5008 (DLAB = 0) 0xFFF8_5808 (DLAB = 0) R R Interrupt Status Register 0 Interrupt Status Register 1 0x0000_00C1 0x0000_00C1 31 23 15 7 FIFO enabled 30 22 14 6 FIFO enabled 29 21 13 5 SCPSNT 28 RESERVED 27 19 11 3 INTS2 26 18 10 2 INTS1 25 17 9 1 INTS0 24 16 8 0 Interrupt pending 20 RESERVED 12 RESERVED 4 SCPTI This register contains mainly interrupt status including transmission-related interrupts and SCPSNT toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 8 when BDLAB = 0) and SCPSNT line status. - 435 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:6] [5] RESERVED SCPSNT Smart card present line status. User may poll this bit to see SCPSNT pin's voltage level 0 = Smart card has been remove from the reader 1 = Smart card IC is contact with the reader SCPSNT toggle interrupt status. A rising/falling edge of SCPSNT signal triggers an interrupt and set this status bit if ESCPTI (IER bit 3) is set to "1" to enable SCPSNT toggle interrupt. 0= No SCPSNT toggle interrupt. 1 = SCPSNT toggle interrupt occurs. Interrupt Status bit 2 ~0 The combination indicates which kind of transmission-related interrupt has occurred. Refer to the following table for details. ISR bit Interrupt set and function 3210 Priority Interrupt Interrupt source Clear interru type 0001 No interrupt pending 1010 first Card SCPTI =1 Read ISR insert or remove Read SCSR 1110 second TIME1. TO2 =1 OUT 2. TO1 =1 interrupt 3. TO0 =1 Read SCSR 0110 third Data 1. OER = 1 receiving 2. PBER = 1 status 3. NSER = 1 4. SBD = 1 0100 fourth RBR data 1. RBR data ready 1. Read RB ready 2. FIFO interrupt active 2. Read RB level reached under ac 1100 fifth FIFO data Receiver FIFO is nonRead RBR time out empty and no activities are occurred in the receiver FIFO during the TOR defined time duration 0010 sixth TBR TBR empty 1. Write dat empty 2. Read ISR sixth) Interrupt pending status bit. This bit is a logical "1" if there is no interrupt pending. If one of the interrupt sources occurs, this bit will be set to a logical "0". 0 = Interrupt pending. 1 = No interrupt occurs. [4] SCPTI [3:1] INTS2 INTS0 ~ [0] Interrupt pending - 436 - W90P710 Smart Card FIFO control Register (SCHI_SCFR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCFR0 0xFFF8_5008 (DLAB = 0) SCHI_SCFR1 0xFFF8_5808 (DLAB = 0) W W Interrupt Status Register 0 Interrupt Status Register 1 0x0000_0000 0x0000_0000 31 23 15 7 RxTL1 30 22 14 6 RxTL0 29 21 13 5 PEC2 28 RESERVED 27 19 11 3 PEC0 26 18 10 2 TxFRST 25 17 9 1 RxFRST 24 16 8 0 Reserved 20 RESERVED 12 RESERVED 4 PEC1 BITS DESCRIPTIONS [31:8] RESERVED Receiver FIFO active Threshold Level control bits. These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an interrupt is activated to notify host to read data from FIFO. Default to be 00b. [7:6] RxTL1, RxTL0 RxTL1 RxTL0 Rx FIFO Interrupt Active Level (Bytes) 0 0 1 1 0 1 0 1 01 04 08 14 - 437 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS [5:3] PEC2, PEC1, PEC0 Parity Error Count. Bits PEC2, PEC1 and PEC0 determine the number of allowed repetitions in reception or in transmission before setting bit PBER in SCSR. The value 000 indicates that, if only one parity error has occurred, bit PE is set; the value 111 indicate that bit PE will be set after 8 parity errors. In protocol T =0: If a correct character is received before the programmed error number is reached, the error counter will be reset If the programmed number of allowed parity errors is reached, bit PBER in register SCSR will be set as long as register SCSR has not been read. If a transmitted character has been NAK by the card, then our smart card host interface will automatically re-transmit it a number of times equal to the value programmed in bits PEC2, PEC1 and PEC0. In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then the automatic re-transmission is invalided; the character manually rewritten in register TBR will start at 13.5 ETU. In protocol T= 1: The error counter has no action; bit PE is set at the first incorrectly received character. Transmitter FIFO Reset control bit. Setting this bit to a logical "1" resets the transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". Receiver FIFO Reset control bit. Setting this bit to a logical "1" resets the receiver FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". - [2] TxFRST [1] [0] RxFRST RESERVED Smart Card Control Register (SCHI_SCCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCCR0 SCHI_SCCR1 0xFFF8_500C 0xFFF8_580C R/W R/W Smart Card Control Register 0 Smart Card Control Register 1 0x0000_0018 0x0000_0018 - 438 - W90P710 31 23 15 7 BDLAB 30 22 14 6 DIR 29 21 13 5 NSBE 28 20 12 4 EPE 27 19 11 3 PROT 26 18 10 2 Reserved 25 17 9 1 Reserved 24 16 8 0 Reserved RESERVED RESERVED RESERVED BITS DESCRIPTIONS [31:8] RESERVED Baud rate Divisor Latch Access Bit. When this bit is set to a logical "1", users may access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of baudrate generator during a read/write operation. A special Smart Card ID can also be read at base address + 8 when BDLAB is "1". When this bit is set to "0", accesses to base address + 0, 4 or 8 refer to RBR/TBR, IER or ISR/SCFR respectively. DIRect convention When set as a `0' or `1' will receive data in the direct convention or indirect convention manner respectively. In other words, the controller will need to have this bit set to a `1' if the first byte of the ATR process is 3F (i.e. Indirect convention) and a `0' if the first byte is 3B (i.e. Direct convention). Silent Byte Enable. Receiver detect the data byte, parity bit and stop bit are all zero Even Parity Enable. This bit is only available when bit 3 of SCCR is programmed to "1". It prescribes number of logical 1s in a data word including parity bit. When this bit is set to "1", even parity is required for transmission and reception. Odd parity is demanded when this bit is set to "0". In contrast to its UART counterpart, Smart Card Control Register only controls parity bit setting because data length is fixed at 8-bit long for Smart Card interface protocol. Protocol. [7] BDLAB [6] DIR [5] NSBE [4] EPE [3] [2:0] Protocol RESERVED Bit PROT is set if the protocol is T = 1 (asynchronous) and bit PROT = 0 if the protocol is T = 0. - - 439 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Smart Card Host Clock Base Register (SCHI_CBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_CBR0 SCHI_CBR1 31 23 15 7 0xFFF8_5010 0xFFF8_5810 30 22 14 6 29 21 13 5 R/W R/W Clock base Register 0 Clock base Register 1 28 RESERVED 0x0000_000C 0x0000_00OC 26 18 10 2 25 17 9 1 24 16 8 0 27 19 11 3 20 RESERVED 12 RESERVED 4 8-bit clock base Data BITS DESCRIPTIONS [31:8] RESERVED Clock Base value. It specifies number of internal sampling clock pulses for a data bit. Default to be 0Ch. This register combining with BLH and BLL (baud rate latches) determine internal sampling clock frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh which mean SCCLK clock frequency is 372 (12 x 31) times of internal sampling clock frequency. The default values of CBR, BLH and BLL are corresponding to default values of transmission factors F and D specified in ISO/IEC 7816-3. The value of 0Ch of CBR means there're 12 sampling clock pulses to detect a 1-etu (elementary time unit) data bit on SCIO signal. It is recommended that user sets CBR to be around 16 to maintain better data integrity and transmission stability. [7:0] CBR Smart Card Host Status Register (SCHI_SCSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCSR0 SCHI_SCSR1 0xFFF8_5014 0xFFF8_5814 R R Smart card Status Register 0 Smart card Status Register 1 0x0000_0060 0x0000_0060 - 440 - W90P710 31 23 15 7 SC_RESET 30 22 14 6 TSRE 29 21 13 RESERVED 28 RESERVED 27 19 11 3 NSER 26 18 10 TOF2 2 PBER 25 17 9 TOF1 1 OER 24 16 8 TOF0 0 RDR 20 RESERVED 12 4 SBD 5 TBRE BITS DESCRIPTIONS [31:11] RESERVED RESERVED TOF2 is Time-Out Flag of Timer2. When Timer 2 time out, it will set the FLAG (TOF2) When host reads SCSR, it clears this bit to "0". TOF1 is Time-Out Flag of Timer1. When Timer 1 time out, it will set the FLAG (TOF1) When host reads SCSR, it clears this bit to "0". TOF0 is Time-Out Flag of Timer0. When Timer 0 time out, it will set the FLAG (TOF0) When host reads SCSR, it clears this bit to "0". SC_RESET pin status This bit reflects the RESET pin high or low. Transmitter Shift Register Empty This bit is set to "1" when transmitter shift register is empty. Transmitter Buffer Register Empty In non-FIFO mode, this bit will be set to a logical 1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or FIFO. Silent Byte Detected This bit is set to "1" to indicate that received data byte are kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". TOF2, [10:8] TOF1, TOF0 [7] [6] SC_RESET TSRE [5] TBRE [4] SBD - 441 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS [3] NSER No Stop bit Error This bit is set to "1" to indicate that received data has no stop bit. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". Parity Bit Error This bit is set to "1" to indicate that parity bit of received data is wrong. In FIFO mode, it indicates the same condition for the data on top of the FIFO. When host reads SCSR, it clears this bit to "0". Overrun Error This bit is set to "1" to indicate previously received data is overwritten by the next received data before it is read by host. In FIFO mode, it indicates the same condition instead of FIFO full. When host reads SCSR, it clears this bit to "0". Receiver Data Ready This bit is set to "1" to indicate received data is ready to be read by host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is cleared to "0". [2] PBER [1] OER [0] RDR Smart Card Host Guard Time Register (SCHI_GTR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_GTR0 SCHI_GTR1 31 23 15 7 0xFFF8_5018 0xFFF8_5818 30 22 14 6 29 21 13 5 R/W R/W 28 20 12 4 Guard time Register 0 Guard time Register 1 27 19 11 3 GTR[7:0] 0x0000_0001 0x0000_0001 25 17 9 1 24 16 8 0 26 18 10 2 RESERVED RESERVED RESERVED BITS DESCRIPTIONS [31:8] RESERVED Guard Time Register value. This register specifies number of stop bits appended in the end of data byte. Bit 7 ~ 0: Guard time values. Default to be 01h. - 442 - [7:0] GTR W90P710 Smart Card Host Extended Control Register (SCHI_ECR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_ECR0 SCHI_ECR1 31 23 15 7 Reserved 0xFFF8_501C 0xFFF8_581C 30 22 14 6 SCKFS2 29 21 13 5 SCKFS1 R/W R/W 28 Extended Control Register 0 Extended Control Register 1 27 19 11 3 CLKSTP 26 18 10 2 CLKSTPL 25 17 9 1 0x0000_0052 0x0000_0052 24 16 8 0 Reserved RESERVED 20 RESERVED 12 RESERVED 4 SCKFS0 BITS DESCRIPTIONS [31:7] RESERVED SCCLK Frequency Selection bit 2, 1 and 0. They select working clock frequency as following table. Default values are 05h. SCKFS0, SCKFS1, SCKFS2 SCCLK frequency 000 80MHz 001 40 MHz 010 20 MHz 011 10 MHz 100 5 MHz 101 2.5 MHz 110 1.25 MHz Clock Stop voltage Level 0 = SCCLK stops at low if CLKSTP is also set to "0". 1 = SCCLK stops at high if CLKSTP is also set to "1". Clock Stop control bit Setting "1" to this bit stops SCCLK at a voltage level specified by CLKSTPL (bit 3 of ECR). - [6:4] SCKFS2, SCKFS1, SCKFS0 [3] CLKSTPL [2] [1:0] CLKSTP RESERVED - 443 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Smart Card Host Test Mode Register (SCHI_TMR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TMR0 SCHI_TMR1 0xFFF8_5020 0XFFF8_5820 R/W R/W Test mode Register 0 Test mode Register 1 0x0000_0000 0x0000_0000 This 8 bit register is added in order to allow better testability of the Smart Card host. Currently only bit 1 is utilized. In the future, other bits can be used to program the host to improve testability on the testing platform. 31 23 15 7 30 22 14 6 29 21 13 5 RESERVED 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 SCRST_L Reserved - 444 - W90P710 BITS DESCRIPTIONS [31:2] RESERVED Smart card Reset pin control bit Software driver controls this bit directly which in turn determines the SCRST_L signal to the Smart Card. `0' or `1' in this bit drives `0' or `1' respectively on the SCRST_L signal. This feature was first added to allow the SCRST_L to be pulled high at a quicker rate during the reset phase to improve testability. However, upon the attempt to further improve the capability of the Smart Card host, it was found that this bit holds the key in solving one of the major problems of this design. Originally, the SCRST_L signal is pulled high automatically after a fixed period of time (via the use of a hardware counter) when the card is inserted. However, there have been many cases where this signal is pulled high even before power is supplied to the card, which is a clear violation to the ISO 7816 specification. This as a result causes non valid ATR to be read by the host during the initial insertion of the card. Earlier versions of this IP rectified this problem by having the software ignore the invalid ATR during the initial insertion and do either a warm or cold setup to capture the true ATR on its second try. This bit allows a lot of flexibility to fix the problem mentioned above. Software driver now has the ability to determine when the SCRST_L is to be pulled either high or low, avoiding this problem which has plagued earlier versions. With this modification, software ensures that the SCRST_L signal is pulled high only after the power is supplied to the card, thus allowing the true ATR to be always read during the initial insertion of the card. - [1] SCRST_L [0] RESERVED Smart Card Host Time-out configuration Register (SCHI_TOC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOC0 SCHI_TOC1 0xFFF8_5028 0xFFF8_5828 R/W R/W Time out Configuration Register 0 Time out Configuration Register 1 0x0000_0000 0x0000_0000 - 445 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 RESERVED 29 21 13 5 TOC4 28 RESERVED 27 19 11 nDBGACK_EN2 3 26 18 10 TOC8 2 TOC2 25 17 9 TOC7 1 TOC1 24 16 8 TOC6 0 TOC0 20 RESERVED 12 4 6 nDBGACK_EN1 TOC5 TOC3 nDBGACK_EN0 BITS DESCRIPTIONS [31:12] RESERVED ICE Debug mode Acknowledge enable for time-out counter 2 [11] nDBGACK_EN2 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held. - 446 - W90P710 Continued BITS DESCRIPTIONS TOC8, TOC7, TOC6 (Time Out Configuration) control 24 bit timeout counter 2 configuration. TOC8, TOC7, TOC6 value 000 001 OPERATION MODE 010 TOC8, [10:8] TOC7, TOC6 011 100 24 bit counter 2 is stopped Counting the value stored in register TOIR 2 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO2 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. Counter 2 starts counting the content of register TOIR2 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 2 reaches its terminal count, an interrupt is given if enable. Bit TO2 in register SCSR is set. The counter is reloaded with TOIR2 and starts counting on each subsequent START bit. It is possible to change the content of TOIR2 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, Counter 2 starts counting the content of register TOIR2 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 2 reaches its terminal count, an interrupt is given if enable. Bit TO2 in register SCSR is set. The count is stopped by writing 000b in register TOC, Same as value 000b, except that counter 2 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC ICE Debug mode Acknowledge enable for time-out counter 1 0 = When DBGACK is high, the timer clock will be held [7] nDBGACK_EN1 1= No matter what DBGACK is high or not, the timer clock will not be held - 447 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS TOC5, TOC4, TOC3 (Time Out Configuration) control 16 bit timeout counter 1 configuration. TOC5, TOC4, TOC3 value 000 001 OPERATION MODE TOC5, [6:4] TOC4, TOC3 010 011 100 16 bit counter 1 is stopped Counting the value stored in register TOIR 1 is started after 0 written in register in register TOC. An interrupt is given if enab bit TO1 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register T should be stopped before reloading new values in register TO Counter 1 starts counting the content of register TOIR1 on the START bit (reception or transmission) detected on the pin I/O 010b is written in register TOC. When counter 1 reaches its te count, an interrupt is given if enable. Bit TO1 in register SCSR The counter is reloaded with TOIR1 and starts counting on ea subsequent START bit. It is possible to change the content of during a count; the current count will not be affected and the count value will be taken into account at the next START bit. count is stopped by writing 000b in register TOC, Counter 1 starts counting the content of register TOIR1 on the START bit (reception or transmission) detected on the pin I/O 010b is written in register TOC. When counter 1 reaches its te count, an interrupt is given if enable. Bit TO1 in register SCSR The count is stopped by writing 000b in register TOC, Same as value 000b, except that counter 1 will be stopped at of the 12th ETU following the first START bit detected after 10 been written in register TOC ICE Debug mode Acknowledge enable for time-out counter 0 [3] nDBGACK_EN0 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held - 448 - W90P710 Continued BITS DESCRIPTIONS TOC5, TOC4, TOC3 (Time Out Configuration) control 8 bit time-out counter 0 configuration. TOC2, TOC1, TOC0 value 000 001 OPERATION MODE TOC2, [2:0] TOC1, TOC0 010 011 100 8 bit counter 0 is stopped Counting the value stored in register TOIR 0 is started after written in register in register TOC. An interrupt is given if en and bit TO0 is set within register SCSR when the terminal c reached. The counter is stopped by writing 000b in register and should be stopped before reloading new values in regis TOC. Counter 0 starts counting the content of register TOIR0 on t START bit (reception or transmission) detected on the pin I/ 010b is written in register TOC. When counter 0 reaches its count, an interrupt is given if enable. Bit TO0 in register SCS set. The counter is reloaded with TOIR0 and starts counting each subsequent START bit. It is possible to change the co TOIR0 during a count; the current count will not be affected new count value will be taken into account at the next STAR The count is stopped by writing 000b in register TOC, Counter 0 starts counting the content of register TOIR0 on t START bit (reception or transmission) detected on the pin I/ 010b is written in register TOC. When counter 0 reaches its count, an interrupt is given if enable. Bit TO0 in register SCS set. The count is stopped by writing 000b in register TOC, Same as value 000b, except that counter 0 will be stopped end of the 12th ETU following the first START bit detected a has been written in register TOC - 449 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Smart Card Host Time-out Initial Register 0 (SCHI_TOIR 0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR0_0 SCHI_TOIR0_1 0xFFF8_502C 0xFFF8_582C R/W R/W 8 bit Time out initial Register 0 8 bit Time out initial Register 1 0x0000_0000 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 TOIR0[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8 bit Time Out Initial Register 0 The value to load in register TOIR 0 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 8 bit time-out initial register used to initial loading value when every start counting. [7:0] TOIR0 Smart Card Host Time-out Initial Register 1 (SCHI_TOIR 1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR1_0 SCHI_TOIR1_1 0xFFF8_5030 0xFFF8_5830 R/W R/W 16 bit Time out initial Register 0 16 bit Time out initial Register 1 0x0000_0000 0x0000_0000 - 450 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 TOIR1[15:8] 4 TOIR1[7:0] BITS DESCRIPTIONS [31:16] RESERVED 16 bit Time Out Initial Register 1 The value to load in register TOIR 1 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 16 bit time-out initial register used to initial loading value when every start counting. [15:0] TOIR1 Smart Card Host Time-out Initial Register 2 (SCHI_TOIR 2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR2_0 SCHI_TOIR2_1 31 23 15 7 0xFFF8_5034 0xFFF8_5834 30 22 14 6 29 21 13 5 R/W R/W 24 bit Time out initial Register 0 24 bit Time out initial Register 1 28 RESERVED 0x0000_0000 0x0000_0000 25 17 9 1 24 16 8 0 27 19 11 3 26 18 10 2 20 TOIR2[23:16] 12 TOIR2[15:8] 4 TOIR2[7:0] BITS DESCRIPTIONS [31:24] RESERVED 24 bit Time Out Initial Register 2 The value to load in register TOIR 2 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 24 bit time-out initial register used to initial loading value when every start counting. [23:0] TOIR2 - 451 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Smart Card Host Time-Out Data Register 0 (SCHI_TODR0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOD0_0 SCHI_TOD0_1 31 23 15 7 0xFFF8_5038 0xFFF8_5838 30 22 14 6 R R 29 21 13 5 8 bit Time out data Register 0 8 bit Time out data Register 1 28 RESERVED 0x0000_00FF 0x0000_00FF 25 17 9 1 24 16 8 0 27 19 11 3 26 18 10 2 20 RESERVED 12 RESERVED 4 TOD0[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8 bit Time Out Data count Register 0 The value showing in register TOD 0 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 8 bit time-out data register used to show the current counting value. [7:0] TOD0 Smart Card Host Time-Out Data Register 1 (SCHI_TODR1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOD1_0 SCHI_TOD1_1 31 23 15 7 0xFFF8_503C 0xFFF8_583C 30 22 14 6 29 21 13 5 R R 16 bit Time out Data Register 0 16 bit Time out Data Register 1 28 RESERVED 0x0000_00FF 0x0000_00FF 25 17 9 1 24 16 8 0 27 19 11 3 26 18 10 2 20 RESERVED 12 TOD1[15:8] 4 TDO1[7:0] - 452 - W90P710 BITS DESCRIPTIONS [31:16] RESERVED 16 bit Time Out Data count Register 1 The value showing in register TOD 1 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 16 bit time-out data register used to show the current counting value. [15:0] TOD1 Smart Card Host Time-Out Data Register 2 (SCHI_TODR2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOD2_0 SCHI_TOD2_1 0xFFF8_5040 0xFFF8_5840 R R 24 bit Time out Data Register 0 24 bit Time out Data Register 1 0x0000_00FF 0x0000_00FF 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 TOD2[23:16] 12 TOD2[15:8] 4 TDO2[7:0] BITS DESCRIPTIONS [31:24] RESERVED 24 bit Time Out Data count Register 2 The value to load in register TOD 2 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 24 bit time-out data register used to show the current counting value. [23:0] TOR2 - 453 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR) Register SCHI_BTOR0 SCHI_BTOR1 31 23 15 7 BTOIE Address 0XFFF8_5044 0XFFF8_5844 30 22 14 6 BTOIC_6 29 21 13 5 BTOIC_5 R/W R/W R/W Description Buffer Time out Data Register 0 Buffer Time out Data Register 1 28 RESERVED Reset Value 0x0000_0000 0x0000_0000 25 17 9 24 16 8 27 19 11 3 BTOIC_3 26 18 10 2 BTOIC_2 20 RESERVED 12 RESERVED 4 BTOIC_4 1 0 BTOIC_1 BTOIC_0 BITS DESCRIPTIONS [31:8] RESERVED Buffer Time Out Interrupt Enable The feature of receiver buffer time out interrupt is enabled only when BTOIE[7] = ERDRI =1 . Buffer Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = ETU) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR[7] = ERDRI =1. A new incoming data word or BRX FIFO empty clear Irpt_TOUT. [7] BTOIE [6:0] BTOIC Smart Card Host Baud Rate Divider Latch Lower Byte (SCHI_BLL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_BLL0 SCHI_BLL1 0XFFF8_5000 (DLAB = 1) 0XFFF8_5800 (DLAB = 1) R/W Baud rate divisor Latch Lower byte Register 0 0x0000_001F R/W Baud rate divisor Latch Lower byte Register 1 0x0000_001F - 454 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 BLL[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8 bit Baud rate divider Latch Low byte register This register combining with BLH and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh. [7:0] BLL Baud Rate Divider Latch Higher Byte (SCHI_BLH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_BLH0 SCHI_BLH1 0XFFF8_5004 (DLAB = 1) 0XFFF8_5804 (DLAB = 1) R/W Baud rate divisor Latch Higher byte Register 0 0x0000_0000 R/W Baud rate divisor Latch Higher byte Register 1 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 BLH[7:0] - 455 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS [31:8] RESERVED 8 bit Baud rate divider Latch High byte register This register combining with BLL and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h. [7:0] BLH SMART CARD ID NUMBER (SCHI_ID) Register SCHI_ID0 SCHI_ID1 Address 0xFFF8_5008 (DLAB = 1) 0XFFF8_5808 (DLAB = 1) R/W Description Reset Value 0x0000_0070 0x0000_0070 R Smart card ID number Register 0 R Smart card ID number Register 1 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 ID[7:0] 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 BITS DESCRIPTIONS [31:8] [7:0] RESERVED ID 8 bit smart card ID number register This register contains a specific value of 70h for driver to identify Smart Card interface. - 456 - W90P710 7.17.3 Functional description The following description uses abbreviations to refer to control/status registers and their contents of Smart Card interface as seen in section 7.12.2 Initialization User needs to program control registers so that ATR (Answer To Reset) data streams can be properly decoded after card insertion. Initialization settings include the following steps where sequential order is irrelevant. 1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3. 2. GTR is programmed with 01h for one stop bit. 3. Set SCFR bit 1 to "1" to reset receiver FIFO. 4. Set EPE bit in SCCR bit 4 to be "1" for EVEN parity, set EPE bit to be "0" for odd parity. 5. Set SCKFS1 and SCKFS0 to "05" to select 2.5 MHz for SCCLK on 80MHz system clock. Most default values of above control bits are designed as specified in initialization step but it is recommended that user performs all the initialization sequence to avoid any ambiguity. The relationship between transmission factors and settings of BLH, BLL and CBR is best described in the following example. F1 (f means SCCLK frequency) 1etu = x Df Therefore, Fd 372 = = (BLH, BLL ) x CBR = 31 x 12 Dd 1 Activation Card insertion pulls up SCPSNT (assuming SCPSNT in ISR bit 5 is active high) and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually applied. SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3). To meet another timing requirement, tc of ISO/IEC 7816-3, a counter based on SCCLK is implemented to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR (Answer To Reset) is detected after 65536 clock cycles from the rising edge of SCRST#. Answer-to-Reset Answer-to-Reset (ATR) is the data streams sent by the card to the interface as an answer to a reset on SCRST# signal. Refer to ISO/IEC 7816-3 for detailed description of ATR. There're two kinds of cards specified in ISO/IEC 7816-3, inverse convention card and direct convention card. Although these two conventions treat logical meanings (0 or 1) of voltage levels (low or high) differently, Winbond's implementation of Smart Card interface decodes a high voltage level data bit as "1" and low voltage level data bit "0" nevertheless and resorts to software to interpret Publication Release Date: January 17, 2005 Revision A.2 - 457 - W90P710 incoming data. Software driver needs to interpret initial character of ATR first to determine which convention is for inserted card and chooses a conversion procedure for it. Subsequent incoming data bytes must be passed through a conversion procedure before actually transfers these data bytes to host. Similar conversion procedure must be applied to outgoing data byte before writing to TBR too. For example, the raw data byte for initial character of inverse-convention ATR would be 3Fh. Software driver therefore needs a conversion procedure to reverse bit-significance and polarity to process subsequent raw data bytes. On the other hand, initial character of direct-convention ATR is 3Bh which needs no conversion procedure to process data byte. Data transfer Software driver might need to configure control registers again based on information contained in ATR before process subsequent data transfer. The following guidelines are provided for programming reference. 1. EPE should be set to "1" for direct-convention card and otherwise for inverse-convention card. 2. BLH, BLL and CBR should be set to comply with Fi and Di. 3. GTR is used for various stop bit requirement of different transmission protocols. 4. Use interrupt resources to control communication sequence. 5. Monitor SCSR for transmission integrity. Cold reset and warm reset Cold reset is achieved by writing a "1" to PWRDN (bit 7 of IER). It deactivates SCPWR# to high. Consequentially, SCRST# is pulled down and SCCLK is stopped. User must write a "0" to PWRDN (bit 7 of IER) to resume Smart Card interface to a normal activation state assuming card is still present. The activation sequence and deactivation sequence are done by internal F.S.M When in a normal activation state, writing a "0" SCRST_L (bit 1 of TMR) will force SC_RST pin to low that will triggers a warm reset. Its effect is similar to cold reset except SCPWR# is kept activated and therefore power supply to card stays on. Power states SCHI employs a sophisticated algorithm to partition Smart Card interface's internal circuits to achieve optimal power utilization. However, users must pay extra care in the design of application circuits following guidelines stated below to prevent potential signal conflict and unnecessary power consumption. There're three power states: disabled state, active state, and power down state. Disabled state is the default state when power is first applied to the IC. SCPWD (Smart Card Power Down) controls whether in active state (SCPWD = 0) or in power down state (SCPWD = 1). Disabled state Smart Card interface is in disabled state initially. Clock is stopped in this state and therefore it is the least power-consuming state. To prevent current leakage from floating connections, it is designed to output a predetermined voltage level on all the I/O pins of Smart Card interface as follows: SCPWR# outputs high to disable power supply to socket; SCRST#, SCCLK, and SCIO output low; - 458 - W90P710 SCPSNT is tri-stated. These I/O conditions also apply to socket in power down state (SCPWD = 1) or deselected socket in idle state. Designers of application circuits must take extra care so that no contention occurs when Smart Card interface is in those power-saving states. Active state Active state is when Smart Card interface is actually performing all its functions: configuration of control and interrupt registers, detection of card insertion/extraction, reception of ATR (Answer To Reset) packet and communication of information between host and card. Refer to section 7.12.3 for detailed function description. This is the most power-consuming state and actual power consumption is dependent on traffic of interface. Power down state Transition from active state to power down state is accomplished by setting SCPWD to "1". Clock is stopped for most internal core circuits except detection circuit for SCPSNT toggle (card insertion/extraction). SCPSNT toggle can interrupt CPU and through this feature Smart Card interface in power down state can be waken up by card insertion/extraction. User may also directly write a "0" to SCPWD to wake up Smart Card interface. Smart Card interface spends a little bit more power to maintain SCPSNT toggle detection circuit in power down state than in disabled state while spares even more power than in active state by stopping clock to core circuit. Users must make sure that all on-going transactions are concluded before putting Smart Card interface into power down state to prevent potential disoperation of internal state machine. - 459 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.18 I2C Interface I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and 400kbps modes are supported directly. For High-speed mode special IOs are needed. If these IOs are available and used, then High-speed mode is also supported. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byteby-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). The I2C Master Core includes the following features: * AMBA APB interface compatible * Compatible with Philips I2C standard, support master mode * Multi Master Operation * Clock stretching and wait state generation * Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer * Software programmable acknowledge bit * Arbitration lost interrupt, with automatic transfer cancellation * Start/Stop/Repeated Start/Acknowledge generation * Start/Stop/Repeated Start detection * Bus busy detection * Supports 7 bit addressing mode * Fully static synchronous design with one clock domain * Software mode I2C - 460 - W90P710 7.18.1 I2C Protocol Normally, a standard communication consists of four parts: 1) START or Repeated START signal generation 2) Slave address transfer 3) Data transfer 4) STOP signal generation SCL SDA S or Sr 1 2 7 8 9 1 2 3-7 8 9 P A6 A5 A4 - A1 A0 R/W ACK D7 D6 D5 - D1 D0 NACK ACK MSB LSB MSB LSB P or Sr Sr Fig. 7.18.1.1 Data transfer on the I2C-bus S SLAVE ADDRESS R/W A DATA A DATA A/A P '0'(write) from master to slave from slave to master data transfer (n bytes + acknowledge) A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition P = STOP condition A master-transmitter addressing a slave receiver with a 7-bit address The transfer direction is not changed S SLAVE ADDRESS R/W A DATA A DATA A P '1'(read) data transfer (n bytes + acknowledge) A master reads a slave immediately after the first byte (address) - 461 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 START or Repeated START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer. A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus. The I2C core generates a START signal when the START bit in the Command Register (CMDR) is set and the READ or WRITE bits are also set. Depending on the current status of the SCL line, a START or Repeated START is generated. STOP signal The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. SCL SDA START condition STOP condition START and STOP conditions Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle. The core treats a Slave Address Transfer as any other write action. Store the slave device's address in the Transmit Register (TxR) and set the WRITE bit. The core will then transfer the slave address on the bus. MSB A6 A5 A4 A3 A2 A1 A0 LSB R/W slave address The first byte after the START procedure - 462 - W90P710 Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-bybyte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle. If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. To write data to a slave, store the data to be transmitted in the Transmit Register (TxR) and set the WRITE bit. To read data from a slave, set the READ bit. During a transfer the core set the I2C_TIP flag, indicating that a Transfer is In Progress. When the transfer is done the I2C_TIP flag is cleared, the IF flag set if enabled, then an interrupt generated. The Receive Register (RxR) contains valid data after the IF flag has been set. The software may issue a new write or read command when the I2C_TIP flag is cleared. SCL SDA data line stable; data valid change of data allowed Bit transfer on the I2C-bus clock pulse for acknowledgement SCL FROM MASTER 1 2 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER S START condition acknowledge Acknowledge on the I2C-bus - 463 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.18.2 I2C Serial Interface Control Registers Map R: read only, W: write only, R/W: both read and write NOTE1: The reset value of I2C_WR0/1 is 0x3F only when SCR, SDR and SER are connected to pull high resistor. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C Interface 0 I2C_CSR0 I2C_CMDR0 I2C_SWR0 I2C_RxR0 I2C_TxR0 I2C_CSR1 I2C_CMDR1 I2C_SWR1 I2C_RxR1 I2C_TxR1 0xFFF8_6000 0xFFF8_6008 0xFFF8_600C 0xFFF8_6010 0xFFF8_6014 0xFFF8_6100 0xFFF8_6108 0xFFF8_610C 0xFFF8_6110 0xFFF8_6114 R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W I2C0 Control and Status Register I2C0 Clock Prescale Register I2C0 Command Register I2C0 Software Mode Control Register I2C0 Data Receive Register I2C0 Data Transmit Register I2C Interface 1 I2C1 Control and Status Register I2C1 Clock Prescale Register I2C1 Command Register I2C1 Software Mode Control Register I2C1 Data Receive Register I2C1 Data Transmit Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 I2C_DIVIDER1 0xFFF8_6104 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 I2C_DIVIDER0 0xFFF8_6004 I2C Control and Status Register 0/1 (I2C_CSR0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_CSR0 I2C_CSR1 31 23 15 7 0xFFF8_6000 R/W I2C Control and Status Register 0 0xFFF8_6100 R/W I2C Control and Status Register 1 30 22 14 Reserved 6 5 Tx_NUM 4 29 21 13 28 20 12 27 Reserved 19 Reserved 11 3 Reserved 10 2 IF 9 18 17 26 25 0x0000_0000 0x0000_0000 24 16 8 I2C_TIP 0 I2C_EN I2C_RxACK I2C_BUSY I2C_AL 1 IE Reserved - 464 - W90P710 BITS DESCRIPTIONS [31:12] [11] Reserved I2C_RxAC K Reserved Received Acknowledge From Slave (Read only) This flag represents acknowledge from the addressed slave. 0 = Acknowledge received (ACK). 1 = Not acknowledge received (NACK). I2C Bus Busy (Read only) 0 = After STOP signal detected. 1 = After START signal detected. Arbitration Lost (Read only) This bit is set when the I2C core lost arbitration. Arbitration is lost when: A STOP signal is detected, but no requested. The master drives SDA high, but SDA is low. Transfer In Progress (Read only) 0 = Transfer complete. 1 = Transferring data. NOTE: When a transfer is in progress, you will not allow writing to any register of the I2C master core except SWR. Transmit Byte Counts These two bits represent how many bytes are remained to transmit. When a byte has been transmitted, the Tx_NUM will decrease 1 until all bytes are transmitted (Tx_NUM = 0x0) or NACK received from slave. Then the interrupt signal will assert if IE was set. 0x0 = Only one byte is left for transmission. 0x1 = Two bytes are left to for transmission. 0x2 = Three bytes are left for transmission. 0x3 = Four bytes are left for transmission. Reserved Interrupt Flag The Interrupt Flag is set when: Transfer has been completed. Transfer has not been completed, but slave responded NACK (in multi-byte transmit mode). Arbitration is lost. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Interrupt Enable 0 = Disable I2C Interrupt. 1 = Enable I2C Interrupt. I2C Core Enable 0 = Disable I2C core, serial bus outputs are controlled by SDW/SCW. 1 = Enable I2C core, serial bus outputs are controlled by I2C core. [10] I2C_BUSY [9] I2C_AL [8] I2C_TIP [5:4] Tx_NUM [3] Reserved [2] IF [1] IE [0] I2C_EN - 465 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_DIVIDER0 I2C_DIVIDER1 0xFFF8_6004 0xFFF8_6104 R/W R/W I2C Clock Prescale Register 0 I2C Clock Prescale Register 1 0x0000_0000 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 DIVIDER[15:8] DIVIDER[7:0] BITS DESCRIPTIONS Clock Prescale Register It is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when the "I2C_EN" bit is cleared. Example: pclk = 32MHz, desired SCL = 100KHz [15:0] DIVIDER prescale = 32 MHz - 1 = 63 ( dec ) = 3 F ( hex ) 5 100 KHz I2C Command Register 0/1 (I2C_CMDR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_CMDR0 0xFFF8_6008 R/W I2C Command Register 0 I2C_CMDR1 0xFFF8_6108 R/W I2C Command Register 1 0x0000_0000 0x0000_0000 - 466 - W90P710 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 START 27 19 11 3 STOP 26 18 10 2 READ 25 17 9 1 WRITE 24 16 8 0 ACK NOTE: Software can write this register only when I2C_EN = 1. BITS DESCRIPTIONS [31:5] [4] [3] [2] [1] Reserved START STOP READ WRITE Reserved Generate Start Condition Generate (repeated) start condition on I2C bus. Generate Stop Condition Generate stop condition on I2C bus. Read Data From Slave Retrieve data from slave. Write Data To Slave Transmit data to slave. Send Acknowledge To Slave When I2C behaves as a receiver, sent ACK (ACK = `0') or NACK (ACK = `1') to slave. [0] ACK NOTE: The START, STOP, READ and WRITE bits are cleared automatically while transfer finished. READ and WRITE cannot be set concurrently. I2C Software Mode Register 0/1(I2C_SWR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_SWR0 I2C_SWR1 0xFFF8_600C 0xFFF8_610C R/W I2C Software Mode Control Register 0 R/W I2C Software Mode Control Register 1 0x0000_003F 0x0000_003F - 467 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 Reserved 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 SDR 27 19 11 3 SCR 26 18 10 2 Reserved 25 17 9 1 SDW 24 16 8 0 SCW Note: This register is used as software mode of I2C. Software can read/write this register no matter I2C_EN is 0 or 1. But SCL and SDA are controlled by software only when I2C_EN = 0. BITS DESCRIPTIONS [31:6] [5] [4] Reserved Reserved SDR Reserved Reserved Serial Interface SDA Status (Read only) 0 = SDA is Low. 1 = SDA is High. Serial Interface SCK Status (Read only) 0 = SCL is Low. 1 = SCL is High. Reserved Serial Interface SDA Output Control 0 = SDA pin is driven Low. 1 = SDA pin is tri-state. Serial Interface SCK Output Control 0 = SCL pin is driven Low. 1 = SCL pin is tri-state. [3] [2] [1] SCR Reserved SDW [0] SCW I2C Data Receive Register 0/1 (I2C_RxR 0/1) REGISTER OFFSET R/W DESCRIPTION RESET VALUE I2C_RXR0 I2C_RXR1 0xFFF8_6010 0xFFF8_6110 R R I2C Data Receive Register 0 I2C Data Receive Register 1 0x0000_0000 0x0000_0000 - 468 - W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Rx [7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:8] [7:0] Reserved Rx Reserved Data Receive Register The last byte received via I2C bus will put on this register. The I2C core only used 8-bit receive buffer. I2C Data Transmit Register 0/1 (I2C_TxR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_TXR0 I2C_TXR1 31 23 15 7 0xFFF8_6014 R/W I2C Data Transmit Register 0xFFF8_6114 R/W I2C Data Transmit Register 30 22 14 6 29 21 13 5 28 Tx [31:24] 20 Tx [23:16] 12 Tx [15:8] 4 Tx [7:0] 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 0x0000_0000 24 16 8 0 - 469 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 BITS DESCRIPTIONS Data Transmit Register The I2C core used 32-bit transmit buffer and provide multi-byte transmit function. Set CSR[Tx_NUM] to a value that you want to transmit. I2C core will always issue a transfer from the highest byte first. For example, if CSR[Tx_NUM] = 0x3, Tx[31:24] will be transmitted first, then Tx[23:16], and so on. [31:0] Tx In case of a data transfer, all bits will be treated as data. In case of a slave address transfer, the first 7 bits will be treated as 7bit address and the LSB represent the R/W bit. In this case, LSB = 1, reading from slave LSB = 0, writing to slave - 470 - W90P710 7.19 Universal Serial Interface The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. This interface can drive up to 2 external peripherals and is seen as the master. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to low active or high active, which depends on the peripheral it's connected. Writing a divisor into DIVIDER register can program the frequency of serial clock output. This master core contains four 32-bit transmit/receive buffers, and can provide burst mode operation. The maximum bits can be transmitted/received is 32 bits, and can transmit/receive data up to four times successive. The USI (Microwire/SPI) Master Core includes the following features: * AMBA APB interface compatible * Support USI (Microwire/SPI) master mode * Full duplex synchronous serial data transfer * Variable length of transfer word up to 32 bits * Provide burst mode operation, transmit/receive can be executed up to four times in one transfer * MSB or LSB first data transfer * Rx and Tx on both rising or falling edge of serial clock independently * 2 slave/device select lines * Fully static synchronous design with one clock domain 7.19.1 USI Timing Diagram The timing diagram of USI is shown as following. mw_ss_o mw_sclk_o MSB (Tx[7]) MSB (Rx[7]) LSB (Tx[0]) LSB (Rx[0]) mw_so_o Tx[6] Tx[5] Tx[4] Tx[3] Tx[2] Tx[1] mw_si_i Rx[6] Rx[5] Rx[4] Rx[3] Rx[2] Rx[1] CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0 Fig. 7.19.1.1 USI Timing Publication Release Date: January 17, 2005 Revision A.2 - 471 - W90P710 mw_ss_o mw_sclk_o LSB (Tx[0]) LSB (Rx[0]) MSB (Tx[7]) MSB (Rx[7]) mw_so_o Tx[1] Tx[2] Tx[3] Tx[4] Tx[5] Tx[6] mw_si_i Rx[1] Rx[2] Rx[3] Rx[4] Rx[5] Rx[6] CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0 Fig. 7.19.1.2 Alternate Phase SCLK Clock Timing 7.19.2 USI Registers Map R: read only, W: write only, R/W: both read and write REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL USI_DIVIDER USI_SSR Reserved USI_Rx0 USI_Rx1 USI_Rx2 USI_Rx3 USI_Tx0 USI_Tx1 USI_Tx2 USI_Tx3 0xFFF8_6200 0xFFF8_6204 0xFFF8_6208 0xFFF8_620C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C R/W R/W R/W N/A R R R R W W W W Control and Status Register Clock Divider Register Slave Select Register Reserved Data Receive Register 0 Data Receive Register 1 Data Receive Register 2 Data Receive Register 3 Data Transmit Register 0 Data Transmit Register 1 Data Transmit Register 2 Data Transmit Register 3 0x0000_0004 0x0000_0000 0x0000_0000 N/A 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last. - 472 - W90P710 USI_Control and Status Register (USI_CNTRL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register 31 23 15 7 30 22 14 SLEEP 6 5 Tx_BIT_LEN 4 29 21 13 28 Reserved 20 Reserved 12 11 Reserved 3 10 LSB 2 Tx_NEG 1 19 18 17 IE 9 27 26 25 0x0000_0004 24 16 IF 8 Tx_NUM 0 GO_BUSY Rx_NEG BITS DESCRIPTIONS [31:18] [17] Reserved IE Reserved Interrupt Enable 0 = Disable USI Interrupt. 1 = Enable USI Interrupt. Interrupt Flag 0 = It indicates that the transfer dose not finish yet. 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Suspend Interval These four bits provide the configuration of suspend interval between two successive transmit/receive in a transfer. The default value is 0x0. When CNTRL [Tx_NUM] = 00, setting this field has no effect on transfer. The desired interval is obtained according to the following equation (from the last falling edge of current sclk to the first rising edge of next sclk): (CNTRL[SLEEP] + 2)*period of SCLK SLEEP = 0x0 ... 2 SCLK clock cycle SLEEP = 0x1 ... 3 SCLK clock cycle ...... SLEEP = 0xe ... 16 SCLK clock cycle SLEEP = 0xf ... 17 SCLK clock cycle [16] IF [15:12] SLEEP - 473 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS [11] Reserved Reserved Send LSB First 0 = The MSB is transmitted/received first (which bit in TxX/RxX register that is depends on the Tx_BIT_LEN field in the CNTRL register). 1 = The LSB is sent first on the line (bit TxX[0]), and the first bit received from the line will be put in the LSB position in the Rx register (bit RxX[0]). Transmit/Receive Numbers This field specifies how many transmit/receive numbers should be executed in one transfer. 00 = Only one transmit/receive will be executed in one transfer. 01 = Two successive transmit/receive will be executed in one transfer. 10 = Three successive transmit/receive will be executed in one transfer. 11 = Four successive transmit/receive will be executed in one transfer. Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. Tx_BIT_LEN = 0x01 ... 1 bit Tx_BIT_LEN = 0x02 ... 2 bits ...... Tx_BIT_LEN = 0x1f ... 31 bits Tx_BIT_LEN = 0x00 ... 32 bits Transmit On Negative Edge 0 = The mw_so_o signal is changed on the rising edge of mw_sclk_o. 1 = The mw_so_o signal is changed on the falling edge of mw_sclk_o. Receive On Negative Edge 0 = The mw_si_i signal is latched on the rising edge of mw_sclk_o. 1 = The mw_si_i signal is latched on the falling edge of mw_sclk_o. Go and Busy Status 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished. NOTE: All registers should be set before writing 1 to the GO_BUSY bit in the CNTRL register. When a transfer is in progress, writing to any register of the USI(Microwire/SPI) master core has no effect. [10] LSB [9:8] Tx_NUM [7:3] Tx_BIT_LEN [2] Tx_NEG [1] Rx_NEG [0] GO_BUSY - 474 - W90P710 USI Divider Register (USI_DIVIDER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 11 3 10 2 9 1 19 18 17 27 26 25 0x0000_0000 24 16 8 0 DIVIDER[15:8] DIVIDER[7:0] BITS DESCRIPTIONS Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output mw_sclk_o. The desired frequency is obtained according to the following equation: [15:0] DIVIDER f sclk = (DIVIDER + 1)* 2 f pclk NOTE: Suggest DIVIDER should be at least 1. USI Slave Select Register (USI_SSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_SSR 0xFFF8_6208 R/W USI Slave Select Register 0x0000_0000 - 475 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 ASS 26 18 10 2 SS_LVL 25 17 9 1 SSR[1:0] 24 16 8 0 BITS DESCRIPTIONS [3] ASS Automatic Slave Select 0 = If this bit is cleared, slave select signals are asserted and deasserted by setting and clearing related bits in SSR register. 1 = If this bit is set, mw_ss_o signals are generated automatically. It means that device/slave select signal, which is set in SSR register is asserted by the USI controller when transmit/receive is started by setting CNTRL[GO_BUSY], and is de-asserted after every transmit/receive is finished. Slave Select Active Level It defines the active level of device/slave select signal (mw_ss_o). 0 = The mw_ss_o slave select signal is active Low. 1 = The mw_ss_o slave select signal is active High. Slave Select Register If SSR[ASS] bit is cleared, writing 1 to any bit location of this field sets the proper mw_ss_o line to an active state and writing 0 sets the line back to inactive state. If SSR[ASS] bit is set, writing 1 to any bit location of this field will select appropriate mw_ss_o line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of mw_ss_o is specified in SSR[SS_LVL]). NOTE: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer. [2] SS_LVL [1:0] SSR - 476 - W90P710 USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_RX0 USI_RX1 USI_RX2 USI_RX3 31 23 15 7 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C R R R R USI Data Receive Register 0 USI Data Receive Register 1 USI Data Receive Register 2 USI Data Receive Register 3 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 30 22 14 6 29 21 13 5 28 Rx [31:24] 20 Rx [23:16] 12 Rx [15:8] 4 Rx [7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and CNTRL[Tx_NUM] is set to 0x0, bit Rx0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same FFs. [31:0] Rx Data Transmit Register 0/1/2/3 (Tx0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_TX0 USI_TX1 USI_TX2 USI_TX3 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C W W W W USI Data Transmit Register 0 USI Data Transmit Register 1 USI Data Transmit Register 2 USI Data Transmit Register 3 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 477 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 Tx [31:24] 20 Tx [23:16] 12 Tx [15:8] 4 Tx [7:0] 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 BITS DESCRIPTIONS Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and the CNTRL[Tx_NUM] is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If CNTRL[Tx_BIT_LEN] is set to 0x00 and CNTRL[Tx_NUM] is set to 0x3, the core will perform four 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0], Tx2[31:0], Tx3[31:0]). NOTE: The RxX and TxX registers share the same flip-flops, which means that what is received from the input data line in one transfer will be transmitted on the output data line in the next transfer if no write access to the TxX register is executed between the transfers. [31:0] Tx - 478 - W90P710 7.20 PWM The W90P710 have 4 channels PWM timers. They can be divided into two groups. Each group has 1 Prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 Dead-Zone generator. They are all driven by PCLK (80 MHz). Each channel can be used as a timer and issue interrupt independently. Two channels PWM timers in one group share the same prescaler. Clock divider provides each channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock signal from clock divider which receives clock from 8-bit prescaler. The 16-bit counter in each channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-bit comparator compares number in counter with threshold number in register loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is enabled, output of two PWM timer in one group is blocked. Two output pin are all used as Dead-Zone generator output signal to control off-chip power device. To prevent PWM driving output pin with unsteady waveform, 16-bit counter and 16-bit comparator are implemented with double buffering feature. User can feel free to write data to counter buffer register and comparator buffer register without generating glitch. When 16-bit down counter reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches zero, if counter is set as toggle mode, it is reloaded automatically and start to generate next cycle. User can set counter as one-shot mode instead of toggle mode. If counter is set as one-shot mode, counter will stop and generate one interrupt request when it reaches zero. The value of comparator is used for pulse width modulation. The counter control logic changes the output level when down-counter value matches the value of compare register. The PWM timer features are shown as below: Two 8-bit prescalers and two clock dividers Four clock selectors Four 16-bit counters and four 16-bit comparators Two Dead-Zone generator 7.20.1 PWM double buffering and reload automatically W90P710 PWM Timers have a double buffering function, enabling the reload value changed for next timer operation without stopping current timer operation. Although new timer value is set, current timer operation still operate successfully. The counter value can be written into PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 and current counter value can be read from PWM_PDR0, PWM_PDR1, PWM_PDR2, PWM_PDR3. Publication Release Date: January 17, 2005 Revision A.2 - 479 - W90P710 The auto-reload operation copies from PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 to down-counter when down-counter reaches zero. If PWM_CNR0~3 are set as zero, counter will be halt when counter count to zero. If auto-reload bit is set as zero, counter will be stopped immediately. 7.20.2 Modulate Duty Ratio The double buffering function allows CMR written at any point in current cycle. The loaded value will take effect from next cycle. 7.20.3 Dead Zone Generator W90P710 PWM is implemented with Dead Zone generator. They are built for power device protection. This function enables generation of a programmable time gap at the rising of PWM output waveform. User can program PWM_PPR [31:24] and PWM_PPR [23:16] to determine the Dead Zone interval. - 480 - W90P710 Dead zone generator operation PWM_out1 PWM_out1_n PWM_out1_DZ PWM_out1_n_DZ Dead zone interval 7.20.4 PWM Timer Start procedure 1. Setup clock selector (PWM_CSR) 2. Setup prescaler & dead zone interval (PWM_PPR) 3. Setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and PWM timer off. (PWM_PCR) 4. Setup comparator register (PWM_CMR) 5. Setup counter register (PWM_CNR) 6. Setup interrupt enable register (PWM_PIER) 7. Enable PWM timer (PWM_PCR) 7.20.5 PWM Timer Stop procedure Method 1 : Set 16-bit down counter(PWM_CNR) as 0, and monitor PWM_PDR. When PWM_PDR reaches to 0, disable PWM timer (PWM_PCR). (Recommended) Method 2 : Set 16-bit down counter(PWM_CNR) as 0. When interrupt request happen, disable PWM timer (PWM_PCR). (Recommended) Method 3 : Disable PWM timer directly (PWM_PCR). (Not recommended) - 481 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.20.6 PWM Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR PWM_CSR PWM_PCR PWM_CNR0 PWM_CMR0 PWM_PDR0 PWM_CNR1 PWM_CMR1 PWM_PDR1 PWM_CNR2 PWM_CMR2 PWM_PDR2 PWM_CNR3 PWM_CMR3 PWM_PDR3 PWM_PIER PWM_PIIR 0xFFF8_7000 0xFFF8_7004 0xFFF8_7008 0xFFF8_700C 0xFFF8_7010 0xFFF8_7014 0xFFF8_7018 0xFFF8_701C 0xFFF8_7020 0xFFF8_7024 0xFFF8_7028 0xFFF8_702C 0xFFF8_7030 0xFFF8_7034 0xFFF8_7038 0xFFF8_703C 0xFFF8_7040 R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/C PWM Prescaler Register PWM Clock Select Register PWM Control Register PWM Counter Register 0 PWM Comparator Register 0 PWM Data Register 0 PWM Counter Register 1 PWM Comparator Register 1 PWM Data Register 1 PWM Counter Register 2 PWM Comparator Register 2 PWM Data Register 2 PWM Counter Register 3 PWM Comparator Register 3 PWM Data Register 3 PWM Interrupt Enable Register PWM Interrupt Indication Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 PWM Prescaler Register (PWM_PPR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR 31 23 15 7 0xFFF8_7000 R/W PWM Prescaler Register 0x0000_0000 30 22 14 6 29 21 13 5 28 DZI1 20 DZI0 12 CP1 4 CP0 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - 482 - W90P710 BITS DESCRIPTIONS [31:24] DZI1 DZI1: Dead zone interval register 1, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 2. DZI0: Dead zone interval register 0, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 0. CP1 : Clock prescaler 1 for PWM Timer channel 2 & 3 [23:16] DZI0 [15:8] CP1 Clock input is divided by (CP1 + 1) before it is fed to the counter. 2 & 3 If CP1=0, then the prescaler 1 output clock will be stopped. CP0 : Clock prescaler 0 for PWM Timer channel 0 & 1 [7:0] CP0 Clock input is divided by (CP0 + 1) before it is fed to the counter. 0 & 1 If CP0=0, then the prescaler 0 output clock will be stopped. PWM Clock Select Register (PWM_CSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_CSR 31 23 15 Reserved 7 Reserved BITS 0xFFF8_7004 R/W PWM Clock Select Register 0x0000_0000 30 22 14 6 29 21 13 CSR3 5 CSR1 28 Reserved 20 Reserved 12 4 27 19 11 Reserved 3 Reserved DESCRIPTIONS 26 18 10 2 25 17 9 CSR2 1 CSR0 24 16 8 0 [14:12] [10:8] [6:4] [2:0] CSR3 CSR2 CSR1 CSR0 Select clock input for channel 3 Select clock input for channel 2. Select clock input for channel 1 Select clock input for channel 0 - 483 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 CSR3 INPUT CLOCK DIVIDED BY 000 001 010 011 100 2 4 8 16 1 PWM Control Register (PWM_PCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PCR 31 23 15 PCR15 7 PCR07 0xFFF8_7008 R/W PWM Control Register 0x0000_0000 30 22 Reserved 14 PCR14 6 PCR06 29 21 13 PCR13 5 PCR05 28 Reserved 20 12 PCR12 4 PCR04 27 19 PCR19 11 PCR11 3 PCR03 26 18 PCR18 10 PCR10 2 PCR02 25 17 PCR17 9 PCR09 1 PCR01 24 16 PCR16 8 PCR08 0 PCR00 BITS DESCRIPTIONS Channel 3 toggle/one shot mode [19] PCR 19 1 = toggle mode 0 = one shot mode Channel 3 Inverter on/off [18] PCR 18 1 = inverter on 0 = inverter off [17] PCR 17 Reserved Channel 3 enable/disable [16] PCR 16 1 = enable 0 = disable - 484 - W90P710 Continued BITS DESCRIPTIONS Channel 2 toggle/one shot mode [15] PCR 15 1 = toggle mode 0 = one shot mode Channel 2 Inverter on/off [14] PCR 14 1 = inverter on 0 = inverter off [13] PCR 13 Reserved Channel 2 enable/disable [12] PCR 12 1 = enable 0 = disable Channel 1 toggle/one shot mode [11] PCR 11 1 = toggle mode 0 = one shot mode Channel 1 Inverter on/off [10] PCR 10 1 = inverter on 0 = inverter off [09] PCR 09 Reserved Channel 1 enable/disable [08] PCR 08 1 = enable 0 = disable [07] [06] PCR 07 PCR 06 Reserved Reserved Dead-Zone generator 1 enable/disable [05] PCR 05 1 = enable dead-zone generator 0 = disable dead-zone generator Dead-Zone generator 0 enable/disable [04] PCR 04 1 = enable dead-zone generator 0 = disable dead-zone generator - 485 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTIONS Channel 0 toggle/one shot mode [03] PCR 03 1 = toggle mode 0 = one shot mode Channel 0 Inverter on/off [02] PCR 02 1 = inverter on 0 = inverter off [01] PCR 01 Reserved Channel 0 enable/disable [00] PCR 00 1 = enable 0 = disable PWM Counter Register 0/1/2/3 (PWM_CNR0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_CNR0 PWM_CNR1 PWM_CNR2 PWM_CNR3 31 23 15 7 0xFFF8_700C 0xFFF8_7018 0xFFF8_7024 0xFFF8_7030 R/W PWM Counter Register 0 R/W PWM Counter Register 1 R/W PWM Counter Register 2 R/W PWM Counter Register 3 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 CNRx[15:8] CNRx[7:0] - 486 - W90P710 BITS DESCRIPTIONS [31:16] Reserved CNR: PWM counter/timer buffer. Inserted data range: 65535~0. Unit: 1 PWM clock cycle Note 1: One PWM counter countdown interval = CNR + 1.If CNR is loaded as zero, PWM counter will be stopped. Note 2: Programmer can feel free to write data to CNR at any time, and it will be reloaded when PWM counter reaches zero. [15:0] CNRx PWM Comparator Register 0/1/2/3 (PWM_CMR0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_CMR0 PWM_CMR1 PWM_CMR2 PWM_CMR3 31 23 15 7 0xFFF8_7010 0xFFF8_701C 0xFFF8_7028 0xFFF8_7034 30 22 14 6 29 21 13 5 R/W PWM Comparator Register 0 R/W PWM Comparator Register 1 R/W PWM Comparator Register 2 R/W PWM Comparator Register 3 28 Reserved 20 Reserved 12 4 CMRx[7:0] 11 3 10 2 9 1 19 18 17 27 26 25 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 24 16 8 0 CMRx[15:8] BITS DESCRIPTIONS [31:16] Reserved CMR: PWM comparator register Inserted data range: 65535~0. CMR is used to determine PWM output duty ratio. Note 1: PWM duty = CMR + 1.If CMR is loaded as zero, PWM duty = 1 Note 2: Programmer can feel free to write data to CMR at any time, and it will be reloaded when PWM counter reaches zero. [15:0] CMRx - 487 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PDR0 PWM_PDR1 PWM_PDR2 PWM_PDR3 31 23 15 7 0xFFF8_7014 0xFFF8_7020 0xFFF8_702C 0xFFF8_7038 30 22 14 6 29 21 13 5 R R R R PWM Data Register 0 PWM Data Register 1 PWM Data Register 2 PWM Data Register 3 28 Reserved 20 Reserved 12 4 PDRx[7:0] 11 3 10 2 9 1 19 18 17 27 26 25 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 24 16 8 0 PDRx[15:8] BITS DESCRIPTIONS [31:16] [15:0] Reserved PDRx PDR: PWM Data register. User can monitor PDR to get current value in 16-bit down counter. PWM Interrupt Enable Register (PWM_PIER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PIER 31 23 15 7 0xFFF8_703C 30 22 14 6 Reserved 29 21 13 5 R/W PWM Interrupt Enable Register 28 Reserved 20 Reserved 12 Reserved 4 3 PIER3 2 PIER2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 PIER0 PIER1 - 488 - W90P710 BITS DESCRIPTIONS [31:4] [3] Reserved PIER3 Enable/Disable PWM counter channel 3 interrupt request 1 = enable 0 = disable Enable/Disable PWM counter channel 2 interrupt request 1 = enable 0 = disable Enable/Disable PWM counter channel 1 interrupt request 1 = enable 0 = disable Enable/Disable PWM counter channel 0 interrupt request 1 = enable 0 = disable [2] PIER2 [1] PIER1 [0] PIER0 PWM Interrupt Indication Register (PWM_PIIR) REGISTER ADDRESS R/W/C DESCRIPTION RESET VALUE PWM_PIIR 31 23 15 7 0xFFF8_7040 30 22 14 6 Reserved 29 21 13 5 R/C PWM Interrupt Indication Register 28 Reserved 20 Reserved 12 Reserved 4 3 PIIR3 DESCRIPTIONS 0x0000_0000 25 17 9 1 PIIR1 24 16 8 0 PIIR0 27 19 11 26 18 10 2 PIIR2 BITS [3] [2] [1] [0] PIIR3 PIIR2 PIIR1 PIIR0 PWM counter channel 3 interrupt flag PWM counter channel 2 interrupt flag PWM counter channel 1 interrupt flag PWM counter channel 0 interrupt flag Note: User can clear each interrupt flag by writing a zero to corresponding bit in PIIR - 489 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.21 Keypad Interface W90P710 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input. KPI scans an array up to 16x8 with an external 4 to 16 decoder. It can also be programmed to scan 8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the scan signals are dived by W90P710 itself. For minimum pin counts application, an auxiliary priority encoder (TTL 74148) can be used to encode 8 columns input to 3 binary code and one indicator flag. Total 8 pins are required to implement 16x8 key scan. Any 1 or 2 keys in the array that pressed are debounced and encoded. The keypad controller scan key matrix from ROW0 COL 0 1 2 .... 7, ROW1 COL 0 1 2... 7 till to ROW 16 (or ROW 8 or ROW 4) COL 0 0 1 .... 7. If more than 2 keys are pressed, only the keys or apparent keys in the array with the lowest address will be decoded. KPI also supports 2-keys scan interrupt and specified 3-keys interrupt or chip reset. If the 3 pressed keys matches with the 3 keys defined in KPI3KCONF, it will generate an interrupt or chip reset to nWDOG reset output depend on the ENRST setting. The interrupt is generated whenever the scanner detects a key is pressed. The interrupt conditions are 1 key, 2 keys and 3keys. W90P710 provides two keypad connecting interface. One is allocated in LCD (GPIO30-41) interface, the other is in Ethernet RMII PHY interface and I2C interface 2 SDA1, SCL1 (GPIO42-51). Software should set KPSEL bit in KPICONF register to decide which interface is used as keypad connection port. The keypad interface has the following features: maximum 16x8 array programmable debounce time low-power wakeup mode programmable three-key reset - 490 - W90P710 KPIR[3:0] 4 :16 DECODER W90P710 ROW[[16:0] KPIC[7:0] COL[7:0] 16x8 key pad matrix Fig. 7.21.1 W90P710 Keypad Interface 7.21.1 KeyPad Interface Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPICONF KPI3KCONF KPILPCONF KPISTATUS 0xFFF8_8000 0xFFF8_8004 0xFFF8_8008 0xFFF8_800C R/W R/W R/W R/O Keypad controller configuration Register Keypad controller 3-keys configuration register Keypad controller configuration register low power 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Keypad controller status register - 491 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.21.2 Register Description Keypad Controller Configuration Register (KPI_CONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPICONF 0xFFF8_8000 R/O key pad configuration register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 ENCODE 13 5 28 20 ODEN 12 DBTC 4 PRESCALE 27 19 KPSEL 11 3 26 18 ENKP 10 2 25 17 KSIZE 9 1 24 16 8 0 RESERVED RESERVED BITS DESCRIPTION [31:22] RESERVED Enable Encode Function If an auxiliary 8 to 3 encoder is used to minimize keypad interface pin counts, user can connect encoder data to KPI_COL[2:0] and indicator flag (low active) to KPI_COL[3]. 1 = enable encoder function 0 = default. (8 column inputs) Open Drain Enable If there are more than one key are pressed in the same column, then "short-circuit" will appear between active scan and inactive scan row. Software can set this bit HIGH to enable scan output KPI_ROW[3:0] pins work as "open-drain" to avoid the "short-circuit". 1 = Open drain 0 = push-pull driver Key pad select W90P710 provide two interfaces for keypad function. Software should set this bit to select which interface is used to connect keypad matrix. 1 = pin#23 ~#34 is used as keypad interface 0 = pin #81~88 and #19,#20 are used as keypad interface [21] ENCODE [20] ODEN [19] KPSEL - 492 - W90P710 Continued BITS DESCRIPTION Key pad scan enable [18] ENKP Setting this bit high enable the key scan function. 1 = enable key pad scan 0 = disable key pad scan Key array size KSIZE [17:16] KSIZE 2'b00 2'b01 2'b1x Key array size 4x8, 3x8, 2x8, 1x8 8x8, 7x8, 6x8, 5x8 16x8, 15x8, 14x8, 13x8, 12x8, 11x8, 10x8, 9x8 Debounce terminal count [15:8] DBTC Debounce counter counts the number of consecutive scans that decoded the same keys. When de-bounce counter counter is equal to terminal count it will generate a key scan interrupt. Row scan cycle pre-scale value This value is used to prescale row scan cycle. The prescale counter is clocked by 0.9375MHz clock. Key array scan time = 1.067us x PRESCALE x16 ROWS [7:0] PRESCALE The following example is the scan time for PRESCALE = 0xFA Tscan_time = 1.067us x 250 x16 = 4.268ms If debounce terminal count = 0x05, key detection interrupt is fired in approximately 21.34ms. The array scan time can range from 17.07us to 1.118 sec. - 493 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 16x8 keys matrix 74138 ROW[15:0] COL[7:0] ROW[3:0] W90P710 COL[0] COL[1] COL[2] COL[3] ENCODER A0 A1 A2 GS IN[7:0] 74148 keypad I/F with 8:3 encoder Fig. 7.21.1 Keypad Interface with row decoder and column encoder Keypad Controller 3-keys Configuration Register (KPI3KCONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPI3KCONF 0xFFF8_8004 W/R three-key register configuration 0x0000_0000 31 23 RESERVED 15 RESERVED 7 RESERVED 30 22 14 6 29 21 K32R 13 K31R 5 K30R 28 20 12 4 27 19 11 3 26 18 10 2 25 EN3KY 17 K32C 9 K31C 1 K30C 24 ENRST 16 8 0 RESERVED - 494 - W90P710 BITS DESCRIPTION [31:26] [25] RESERVED EN3KY Enable three-keys detection Setting this bit enables hardware to detect 3 keys specified by software Enable three-key reset Setting this bit enable hardware reset when three-key is detected. [24] ENRST EN3KY 0 1 1 ENRST X 0 1 Function three-key function is disable generate three-key interrupt hardware reset by three-key-reset [23] [22:19] [18:16] [15] [14:11] [10:8] [7] [6:3] [2:0] RESERVED K32R K32C RESERVED K31R K31C RESERVED K30R K30C The #2 key row address The #2 means the row address and the column address is the highest of the specified 3-kyes. The #2 key column address The #1 key row address The #1 means the row address and the column address is the 2nd of the specified 3-kyes. The #1 key column address The #0 key row address The #0 means the row address and the column address is the lowest of the specified 3-kyes. The #0 key column address Application Note: Due to hardware scan from {row[0], col[0]}, {row[0], col[1]}, ..., to {row[15], col[7]} the {K30R,K30C} should be filled the lowest address of the three-keys. For example, if {2,0} {4,6}, {1,3} keys are defined as three-keys. Software should set {K30R, K30C} = {1, 3}, {K31R, K31C} = {2, 0} and {K32R, K32C} = {4, 6}. KeyPad Interface Low Power Mode Configuration Register (KPILPCONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPILPCOF 0xFFF8_8008 W/R Low power configuration register 0x0000_0000 - 495 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 LPWCEN 4 3 2 LPWR DESCRIPTION 27 19 11 26 18 10 25 17 9 1 24 16 WAKE 8 0 RESERVED RESERVED BITS [31:17] RESERVED Lower power wakeup enable Setting this bit enables low power wakeup 1 = wakeup enable 0 = not enable Low power wakeup column enable Specify columns for low power wakeup. For example, if user wants to use keys in row N and column 0, 2, 5 to wake up W90P710, then the LPWCEN should be fill 8'b00100101. Low power wakeup row address Define the row address keys used to wakeup. For 16x8 or 8x8 (with 4:16 or 3:8 decoder) keypad key configuration, LPWR means "Hex" code but for 4x8 (without decoder), LPWR means "binary" code. For example, if user wants to use all keys on row 3 of 16x8 keypad to wakeup W90P710, then 0x3 should be fill into this register but for 4x8 keypad it should be filled as 4'b1000. [16] WAKE [15:8] LPWCEN [7:4] RESERVED [3:0] LPWR Key Pad Interface Status Register (KPISTATUS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPISTATUS 0xFFF8_800C R/O key pad status register 0x0000_0000 - 496 - W90P710 31 23 15 RESERVED 7 RESERVED BITS 30 22 14 6 29 21 INT 13 5 28 RESERVED 20 3KRST 12 KEY1R 4 KEY0R 27 19 PDWAKE 11 3 26 18 3KEY 10 2 25 17 2KEY 9 KEY1C 1 KEY0C 24 16 1KEY 8 0 RESERVED DESCRIPTION [31:22] RESERVED Key interrupt This bit indicates the key scan interrupt is active and that one or two keys have changed status. The interrupt also occur when the three specified keys are detected if ENRST bit in KPI3KFCON is cleared. It will be cleared by hardware automatically when software read KPISTATUS register. 3-Keys reset flag This bit is a record flag for software reference, it will be set after 3keys reset occur. 1 = 3 keys reset 0 = not reset. This bit is cleared while it is read. Power Down Wakeup flag This flag indicates the chip is wakeup from power down by keypad 1 =wakeup up by keypad 0 = not wakeup Specified three-key is detected. This flag indicates specified-three-keys was detected. Software can read this bit to know the keypad interrupt is 3 key or not. Double-key press [21] INT [20] 3KRST [19] PDWAKE [18] 3KEY [17] 2KEY This bit indicates that 2 keys have been detected. Software can read {KEY1R, KEY1C} and {KEY0R, KEY0C} to know which two keys are pressed. - 497 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Continued BITS DESCRIPTION Single-key press [16] [15] 1KEY RESERVED This bit indicates that 1 key has been detected. Software can read {KEY0R, KEY0C} to know which key is pressed. KEY1 row address [14:11] KEY1R This value indicates key1 row address. The keypad controller scan keypad matrix from row 0, column0 1 2 .... 7 and then row1 column 0 1 2 7 so the lowest key address will be stored in {KEY0R, KEY0C}. This register stores the 2nd address, if more than one key is pressed. KEY1 column address This value indicates key1 column address.. KEY1 row address This value indicates key0 row address. This value indicates key0 row address. This value indicates key1 row address. The keypad controller scan keypad matrix from row 0, column0 1 2 .... 7 and then row1 col 0 1 2 ... 7 still to row16 (or 8, or 4) column 0 1 2 ..... 7 so the lowest key address will be stored in {KEY0R, KEY0C}. KEY1 column address This value indicates key0 row address. [10:8] [7] KEY1C RESERVED [6:3] KEY0R [2:0] KEY0C - 498 - W90P710 7.22 PS2 Host Interface Controller W90P710 PS2 host controller interface is an APB slave consisted of PS2 protocol. It is used to connect to your IBM keyboard or other device through PS2 interface. For example, the IBM keyboard will sends scan codes to the host controller, and the scan codes will tell your Keyboard Bios what keys you have pressed or released. Besides Scan codes, commands can also be sent to the keyboard from host. The most common commands would be the setting/resetting of the status indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs). The PS2 interface implements a bi-directional protocol. The keyboard can send data to the Host and the Host can send data to the Keyboard using two PS2 Clock and PS2 Data lines. Both the PS2 Clock and Data lines are Open Collector bi-directional I/O lines. The Host has the ultimate priority over direction. The keyboard is free to send data to the host when both the PS2 Data and PS2 Clock lines are high (Idle). If the host takes the PS2 Clock line low, the keyboard will buffer any data until the PS2 Clock is released, ie goes high. The transmission of data in the forward direction, ie Keyboard to Host is done with a frame of 11 bits. The first bit is a Start Bit (Logic 0) followed by 8 data bits (LSB First), one Parity Bit (Odd Parity) and a Stop Bit (Logic 1). Each bit should be read on the falling edge of the clock. The Keyboard will generate the clock. The frequency of the clock signal typically ranges from 20 to 30 KHz. The Host to Keyboard Protocol is initiated by taking the PS2 data line low. It is common to take the PS2 Clock line low for more than 60us and then the KBD data line is taken low, while the KBD clock line is released. After that, the keyboard will start generating a clock signal on its PS2 clock line. After the first falling edge has been detected, host will load the first data bit on the PS2 Data line. This bit will be read into the keyboard on the next falling edge, after which host place the next bit of data. This process is repeated for the 8 data bits. It will follow an Odd Parity Bit after the data byte. - 499 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 7.22.1 PS2 Host Controller Interface Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2CMD PS2STS 0xFFF8_9000 0xFFF8_9004 R/W R/W RO RO PS2 Host Controller Command Register PS2 Host Controller Status Register 0x0000_0000 0x0000_0000 PS2SCANCODE 0xFFF8_9008 PS2ASCII 0xFFF8_900C PS2 Host Controller RX Scan Code 0x0000_0000 Register PS2 Host Controller RX ASCII Code 0x0000_0000 Register 7.22.2 Register Description PS2 Host Controller Command Register (PS2_CMD) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2CMD 0xFFF8_900 0 30 22 14 6 13 5 29 21 R/W Command register 0x0000_0000 31 23 15 7 28 20 12 11 4 PS2CMD 27 19 26 18 10 25 17 9 TRAP_SHIFT 24 16 8 EnCMD 0 RESERVED RESERVED RESERVED 3 2 1 BITS DESCRIPTIONS [31:10] RESERVED Trap Shift Key Output to Scan Code Register If the shift key scan code (0x12 0r 0x59) is received by host, software can indicate host whether to update to scan code register or not. No ASCII or SCAN codes will be reported for the shift keys if this bit is set. In this condition, host will only report the shift keys at the RX_shift_key bit of Status register and no interrupt will occur for the shift keys. This is useful for those who wish to use the ASCII data stream and don't want to "manually" filter out the shift key codes. This bit is clear by default. [9] TRAP_SHIFT - 500 - W90P710 Continued BITS DESCRIPTIONS Enable write PS2 Host Controller Commands [8] EnCMD This bit enables the write function of Host controller command to device. Set this bit will start the write process of PS2CMD content and hardware will automatically clear this bit while write process is finished. PS2 Host Controller Commands [7:0] PS2CMD This command filed is sent by the Host to the Keyboard. The most common command would be the setting/resetting of the Status Indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs). PS2 Host Controller Status Register (PS2_STS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2STS 31 23 15 7 0xFFF8_9004 30 22 14 6 29 21 13 5 TX_err R/W Status register 28 20 12 4 TX_IRQ 27 19 11 3 26 18 10 2 RESERVED 25 17 9 1 0x0000_0000 24 16 8 0 RX_IRQ RESERVED RESERVED RESERVED RESERVED BITS DESCRIPTIONS [31:6] RESERVED This Transmit Error Status bit indicates software that device doesn't response ACK after Host wrote a command to it. [5] TX_err This bit is valid when TX_IRQ is asserted. It will automatically reset after software starts next command writing process. This bit is read only. This Transmit Complete Interrupt bit indicates software that the process of Host controller writing command to device is finished. Software needs to write one to this bit to clear this interrupt. Publication Release Date: January 17, 2005 Revision A.2 [4] TX_IRQ - 501 - W90P710 Continued BITS DESCRIPTIONS [3:1] Reserved This Receive Interrupt bit indicates software that Host controller receives one byte data from device. This data is stored at PS2_SCANCODE register. Software needs to write one to this bit to clear this interrupt after reading receiving data in RX_SCAN_CODE register. Note that the reception of the Extend (0xE0) and Release (0xF0) scan code will not cause an interrupt by host. The case of the shift key codes will be determined by the TRAP_SHIFT bit of PS2_CMD register. [0] RX_IRQ PS2 Host Controller RX Scan Code Register (PS2_SCANCODE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2SCANCODE 0xFFFF_9008 R/W key pad c RX Scan Code Register 27 26 18 10 RX_shift_key 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 RESERVED 5 28 20 12 4 25 17 9 1 24 16 8 0 RESERVED 19 RESERVED 11 3 RX_releaseRX_extend 2 RX_SCAN_CODE BITS DESCRIPTIONS [31:11] [10] RESERVED RX_shift_key This Receive Shift Key bit indicates that left or right shift key on the keyboard is hold. This bit is read only and will clear by host when the release shift key codes are received. Receive Released Byte When one key has been released, the keyboard will send F0 (hex) to inform Host controller. This bit indicates software that Host controller receives release byte (F0). This bit is read only and will update when host has received next data byte. [9] RX_release - 502 - W90P710 Continued BITS DESCRIPTIONS Receive Extend Byte [8] RX_extend A handful of the keys on keyboard are extended keys and thus require two more scan code. These keys are preceded by an E0 (hex). This bit indicates software that Host controller receives extended byte (E0). This bit is read only and will update when host has received next data byte. PS2 Host Controller Received Data Field This field stores the original data content transmitted from device. This filed is valid when RX_IRQ is asserted. Note that host will not report "Extend" or "Release" scan code to this field and not generate interrupt if they are received by host, i.e. 0xE0 and 0xF0. The case of the shift key codes will be determined by the TRAP_SHIFT bit of PS2_CMD register. [7:0] RX_SCAN_CODE PS2 Host Controller RX ASCII Code Register (PS2_ASCII) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2ASCII 31 23 15 7 0xFFF8_900C 30 22 14 6 R/W 29 21 13 5 key pad c RX ASCII Code Register 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED RESERVED RESERVED RX_ASCII_CODE BITS DESCRIPTIONS [31:8] RESERVED PS2 Host Controller Received Data Filed [7:0] RX_ASCII_CODE This field stores the ASCII data content transmitted from device. Therefore, this part translates the scan code into an ASCII value. It will be read as 0x2E when there is no ASCII code mapped to the scan code stored in RX_SCAN_CODE register. This filed is valid when RX_IRQ is asserted. - 503 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 8. ELECTRICAL SPECIFICATIONS 9. PACKAGE SPECIFICATIONS 176L LQFP (20X20X1.4 mm footprint 2.0mm) - 504 - W90P710 10. APPENDIX A: W90P710 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written System Manager Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PDID ARBCON PLLCON CLKSEL PLLCON1 I2SCKCON 0xFFF0_0000 R Product Identifier Register 0xX090.0710 0x0000_0000 0x0000_2F01 0x1FFF_3FX8 0x0001_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF0_0004 R/W Arbitration Control Register 0xFFF0_0008 R/W PLL Control Register 0xFFF0_000C R/W Clock Select Register 0xFFF0_0010 R/W PLL Control Register 2 0xFFF0_0014 R/W Audio IIS Clock Control Register IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register PMCON USBTxrCON 0xFFF0_0028 R/W Power Manager Control Register 0xFFF0_0030 R/W USB Transceiver Control Register External Bus Interface Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EBICON ROMCON SDCONF0 SDCONF1 SDTIME0 SDTIME1 EXT0CON EXT1CON EXT2CON EXT3CON CKSKEW 0xFFF0_1000 R/W EBI control register 0xFFF0_1004 R/W ROM/FLASH control register 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0xFFF0_100C R/W SDRAM bank 1 configuration register 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0xFFF0_1018 R/W External I/O 0 control register 0xFFF0_101C R/W External I/O 1 control register 0xFFF0_1020 R/W External I/O 2 control register 0xFFF0_1024 R/W External I/O 3 control register 0xFFF0_1F00 R/W Clock skew control register (for testing) 0x0001_0000 0x0000_0XFC 0x0000_0800 0x0000_0800 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_0038 - 505 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Cache Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCNF CAHCON CAHADR 0xFFF0_2000 0xFFF0_2004 0xFFF0_2008 R/W R/W R/W Cache configuration register Cache control register Cache address register 0x0000_0000 0x0000_0000 0x0000_0000 EMC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAMCMR CAMEN CAM0M CAM0L CAM1M CAM1L CAM2M CAM2L CAM3M CAM3L CAM4M CAM4L CAM5M CAM5L CAM6M CAM6L CAM7M CAM7L CAM8M CAM8L CAM9M CAM9L CAM10M CAM10L CAM11M CAM11L 0xFFF0_3000 0xFFF0_3004 0xFFF0_3008 0xFFF0_300C 0xFFF0_3010 0xFFF0_3014 0xFFF0_3018 0xFFF0_301C 0xFFF0_3020 0xFFF0_3024 0xFFF0_3028 0xFFF0_302C 0xFFF0_3030 0xFFF0_3034 0xFFF0_3038 0xFFF0_303C 0xFFF0_3040 0xFFF0_3044 0xFFF0_3048 0xFFF0_304C 0xFFF0_3050 0xFFF0_3054 0xFFF0_3058 0xFFF0_305C 0xFFF0_3060 0xFFF0_3064 R/W CAM Command Register R/W CAM Enable Register R/W CAM0 Most Significant Word Register R/W CAM0 Least Significant Word Register R/W CAM1 Most Significant Word Register R/W CAM1 Least Significant Word Register R/W CAM2 Most Significant Word Register R/W CAM2 Least Significant Word Register R/W CAM3 Most Significant Word Register R/W CAM3 Least Significant Word Register R/W CAM4 Most Significant Word Register R/W CAM4 Least Significant Word Register R/W CAM5 Most Significant Word Register R/W CAM5 Least Significant Word Register R/W CAM6 Most Significant Word Register R/W CAM6 Least Significant Word Register R/W CAM7 Most Significant Word Register R/W CAM7 Least Significant Word Register R/W CAM8 Most Significant Word Register R/W CAM8 Least Significant Word Register R/W CAM9 Most Significant Word Register R/W CAM9 Least Significant Word Register R/W CAM10 Most Significant Word Register R/W CAM10 Least Significant Word Register R/W CAM11 Most Significant Word Register R/W CAM11 Least Significant Word Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 506 - W90P710 EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM12M CAM12L CAM13M CAM13L CAM14M CAM14L CAM15M CAM15L TXDLSA RXDLSA MCMDR MIID MIIDA FFTCR TSDR RSDR DMARFC MIEN MISTA MGSTA MPCNT MRPC MRPCC MREPC DMARFS CTXDSA CTXBSA CRXDSA CRXBSA 0xFFF0_3068 0xFFF0_306C 0xFFF0_3070 0xFFF0_3074 0xFFF0_3078 0xFFF0_307C 0xFFF0_3080 0xFFF0_3084 0xFFF0_3088 0xFFF0_308C 0xFFF0_3090 0xFFF0_3094 0xFFF0_3098 0xFFF0_309C 0xFFF0_30A0 0xFFF0_30A4 0xFFF0_30A8 0xFFF0_30AC 0xFFF0_30B0 0xFFF0_30B4 0xFFF0_30B8 0xFFF0_30BC 0xFFF0_30C0 0xFFF0_30C4 0xFFF0_30C8 0xFFF0_30CC 0xFFF0_30D0 0xFFF0_30D4 0xFFF0_30D8 R/W CAM12 Most Significant Word Register R/W CAM12 Least Significant Word Register R/W CAM13 Most Significant Word Register R/W CAM13 Least Significant Word Register R/W CAM14 Most Significant Word Register R/W CAM14 Least Significant Word Register R/W CAM15 Most Significant Word Register R/W CAM15 Least Significant Word Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC R/W Receive Descriptor Link List Start Address 0xFFFF_FFFC Register 0x0000_0000 R/W MAC Command Register R/W MII Management Data Register R/W FIFO Threshold Control Register W W Transmit Start Demand Register Receive Start Demand Register 0x0000_0000 R/W MII Management Control and Address Register 0x0090_0000 0x0000_0101 Undefined Undefined 0x0000_0800 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_7FFF 0x0000_0000 0x0000_0000 0x0000_0000 R/W Maximum Receive Frame Control Register R/W MAC Interrupt Enable Register R/W MAC Interrupt Status Register R/W MAC General Status Register R/W Missed Packet Count Register R MAC Receive Pause Count Register R R MAC Receive Pause Current Count Register MAC Remote Pause Count Register R/W DMA Receive Frame Status Register 0x0000_0000 R Current Transmit Descriptor Start Address 0x0000_0000 Register R R R Current Transmit Buffer Start Address Register 0x0000_0000 Current Receive Descriptor Start Address 0x0000_0000 Register Current Receive Buffer Start Address Register 0x0000_0000 - 507 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RXFSM TXFSM FSM0 FSM1 DCR DMMIR BISTR 0xFFF0_3200 0xFFF0_3204 0xFFF0_3208 0xFFF0_320C 0xFFF0_3210 0xFFF0_3214 0xFFF0_3300 R R R R Receive Finite State Machine Register Transmit Finite State Machine Register Finite State Machine Register 0 Finite State Machine Register 1 0x0081_1101 0x0101_1101 0x0001_0101 0x1100_0100 0x0000_003F 0x0000_0000 0x0000_0000 R/W Debug Configuration Register R Debug Mode MAC Information Register R/W BIST Mode Register GDMA Registers Map REGISTER ADDRESS R/W DESCRIPTION Channel 0 Control Register Channel 0 Source Base Address Register Channel 0 Destination Base Address Register Channel 0 Transfer Count Register Channel 0 Current Source Address Register Channel 0 Current Destination Address Register RESET VALUE GDMA_CTL0 GDMA_SRCB0 GDMA_DSTB0 GDMA_TCNT0 GDMA_CSRC0 GDMA_CDST0 GDMA_CTCNT 0 GDMA_CTL1 GDMA_SRCB1 GDMA_DSTB1 GDMA_TCNT1 GDMA_CSRC1 GDMA_CDST1 GDMA_CTCNT 1 0xFFF0_4000 0xFFF0_4004 0xFFF0_4008 0xFFF0_400C 0xFFF0_4010 0xFFF0_4014 0xFFF0_4018 0xFFF0_4020 0xFFF0_4024 0xFFF0_4028 0xFFF0_402C 0xFFF0_4030 0xFFF0_4034 0xFFF0_4038 R/W R/W R/W R/W R R R R/W R/W R/W R/W R R R 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Channel 0 Current Transfer Count Register Channel 1 Control Register Channel 1 Source Base Address Register Channel 1 Destination Base Address Register Channel 1 Transfer Count Register Channel 1 Current Source Address Register Channel 1 Current Destination Address Register Channel 1 Current Transfer Count Register - 508 - W90P710 USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE 0x0000_0010 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_2EDF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0628 0x0100_0002 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 OpenHCI Registers HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnbale HcInterruptDisbale HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadEd HcBulkCurrentED HcDoneHeadED HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus [1] HcRhPortStatus [2] 0xFFF0_5000 0xFFF0_5004 0xFFF0_5008 0xFFF0_5010 0xFFF0_5014 0xFFF0_5018 0xFFF0_5020 0xFFF0_5024 0xFFF0_5028 0xFFF0_5030 0xFFF0_5034 0xFFF0_5038 0xFFF0_503C 0xFFF0_5040 0xFFF0_5044 0xFFF0_5048 0xFFF0_5050 0xFFF0_5054 0xFFF0_5058 R Host Controller Revision Register R/W Host Controller Control Register R/W Host Controller Command Status Register R/W Host Controller Interrupt Enable Register R/W Host Controller Interrupt Disable Register R/W Host Controller Communication Area Register R/W Host Controller Control Head ED Register R/W Host Controller Control Current ED Register R/W Host Controller Bulk Head ED Register R/W Host Controller Done Head Register R/W Host Controller Frame Interval Register R R Host Controller Frame Remaining Register Host Controller Frame Number Register 0xFFF0_500C R/W Host Controller Interrupt Status Register 0xFFF0_501C R/W Host Controller Period Current ED Register 0xFFF0_502C R/W Host Controller Bulk Current ED Register R/W Host Controller Periodic Start Register R/W Host Controller Low Speed Threshold Register R/W Host Controller Root Hub Descriptor A Register R/W Host Controller Root Hub Status Register R/W Host Controller Root Hub Port Status [1] R/W Host Controller Root Hub Port Status [2] 0xFFF0_504C R/W Host Controller Root Hub Descriptor B Register USB Configuration Registers TestModeEnable 0xFFF0_5200 R/W USB Test Mode Enable Register R/W USB Operational Mode Enable Register 0x0XXX_XXXX 0x0000_0000 OperationalModeEnable 0xFFF0_5204 - 509 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Device Register Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE USB_CTL VCMD USB_IE USB_IS USB_IC USB_IFSTR USB_ODATA0 USB_ODATA1 USB_ODATA2 USB_ODATA3 USB_IDATA0 USB_IDATA1 USB_IDATA2 USB_IDATA3 USB_SIE USB_ENG USB_CTLS USB_CONFD EPA_INFO 0xFFF0_6000 R/W 0xFFF0_6004 R/W 0xFFF0_6008 R/W 0xFFF0_600 C R USB control register USB class or vendor command register USB interrupt enable register USB interrupt status register USB interrupt status clear register USB interface and string register USB control transfer-out port 0 register USB control transfer-out port 1 register USB control transfer-out port 2 register USB control transfer-out port 3 register USB transfer-in data port0 register USB control transfer-in data port 1 USB control transfer-in data port 2 USB control transfer-in data port 3 USB SIE status Register USB Engine Register USB control transfer status register USB Configured Value register USB endpoint A information register 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0xFFF0_6010 R/W 0xFFF0_6014 R/W 0xFFF0_6018 0xFFF0_601 C 0xFFF0_6020 0xFFF0_6024 R R R R 0xFFF0_6028 R/W 0xFFF0_602 C R/W 0xFFF0_6030 R/W 0xFFF0_6034 R/W 0xFFF0_6038 0xFFF0_603 C 0xFFF0_6040 R R/W R 0xFFF0_6044 R/W 0xFFF0_6048 R/W - 510 - W90P710 0xFFF0_604 C 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 0x0000_000 0 EPA_CTL EPA_IE EPA_IC EPA_IS EPA_ADDR EPA_LENTH EPB_INFO EPB_CTL EPB_IE EPB_IC EPB_IS EPB_ADDR R/W USB endpoint A control register USB endpoint A Interrupt Enable register USB endpoint A interrupt clear register USB endpoint A interrupt status register USB endpoint A address register USB endpoint A transfer length register USB endpoint B information register USB endpoint B control register USB endpoint B Interrupt Enable register USB endpoint B interrupt clear register USB endpoint B interrupt status register USB endpoint B address register 0xFFF0_6050 R/W 0xFFF0_6054 0xFFF0_6058 0xFFF0_605 C W R R/W 0xFFF0_6060 R/W 0xFFF0_6064 R/W 0xFFF0_6068 R/W 0xFFF0_606 C 0xFFF0_6070 0xFFF0_6074 R/W W R 0xFFF0_6078 R/W - 511 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USB Device Register Map, continued REGISTER OFFSET R/W DESCRIPTION RESET VALUE EPB_LENTH EPC_INFO EPC_CTL EPC_IE EPC_IC EPC_IS EPC_ADDR EPC_LENTH EPA_XFER EPA_PKT EPB_XFER EPB_PKT EPC_XFER EPC_PKT 0xFFF0_607C R/W USB endpoint B transfer length register 0xFFF0_6080 0xFFF0_6084 0xFFF0_608C 0xFFF0_6090 0xFFF0_6094 0xFFF0_6098 R/W USB endpoint C information register R/W USB endpoint C control register W R USB endpoint C interrupt clear register USB endpoint C interrupt status register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF0_6 088 R/W USB endpoint C Interrupt Enable register 0x0000_0000 R/W USB endpoint C address register R/W USB endpoint C transfer length register 0xFFF0_609C R/W 0xFFF0_60A0 0xFFF0_60A4 0xFFF0_60A8 R/W R/W R/W USB endpoint A remain transfer length 0x0000_0000 register USB endpoint A remain packet length 0x0000_0000 register USB endpoint B remain transfer length 0x0000_0000 register USB endpoint B remain packet length 0x0000_0000 register USB endpoint C remain transfer length 0x0000_0000 register USB endpoint C remain packet length 0x0000_0000 register 0xFFF0_60AC R/W 0xFFF0_60B0 R/W SDIO Control Register Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE SDGCR SDDSA SDBCR SDGIER SDGISR SDBIST SDCR SDHINI 0xFFF0_7000 0xFFF0_7004 0xFFF0_7008 0xFFF0_700C 0xFFF0_7010 0xFFF0_7014 0xFFF0_7300 0xFFF0_7304 R/W R/W R/W R/W R/W R/W R/W R/W SD Global Control Register SD DMA Register Transfer Starting Address 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0018 SD DMA Byte Count Register SD Global Interrupt Enable Register SD Global Interrupt Status Register SD BIST Register SD Control Register SD Host Initial Register - 512 - W90P710 SDIO Control Register Map, continued REGISTER OFFSET R/W DESCRIPTION RESET VALUE SDIER SDISR SDAUG SDRSP0 SDRSP1 SDBLEN FB0_0 ..... FB0_127 FB1_0 ..... FB1_127 0xFFF0_7308 0xFFF0_730C 0xFFF0_7310 0xFFF0_7314 0xFFF0_7318 0xFFF0_731C 0xFFF0_7400 ..... 0xFFF0_75FC 0xFFF0_7800 ... 0xFFF0_79FC R/W R/W R/W R R R/W R/W SD Interrupt Enable Register SD Interrupt Status Register SD Command Argument Register SD Receive Response Token Register 0 SD Receive Response Token Register 1 SD Block Length Register Flash Buffer 0 0x0000_0000 0x0000_00XX 0x0000_0000 0xXXXX_XXXX 0x0000_XXXX 0x0000_0000 Undefined R/W Flash Buffer 1 Undefined LCDC Control Register Map REGISTER NAME ADDRESS R/W DESCRIPTION RESET VALUE LCDCON LCDIMSC LCDINTS LCDINTC OSDUPSCF VDUPSCF OSDDNSCF VDDNSCF FIFOCON FIFOSTATUS FIFO1PRM FIFO2PRM FIFO1SADDR 0xFFF0_8000 0xFFF0_8004 0xFFF0_8008 0xFFF0_800C 0xFFF0_8010 0xFFF0_8014 0xFFF0_8018 0xFFF0_801C 0xFFF0_8020 0xFFF0_8024 0xFFF0_8028 0xFFF0_802C 0xFFF0_8030 R/W R/W R W R/W R/W R/W R/W R/W R R/W R/W R/W LCD Controller control register Interrupt Mask Set/Clear Register Masked Interrupt Status Register Interrupt Clear Register OSD data Horizontal/Vertical upscaling factor Video image Horizontal/Vertical up-scaling factor OSD data Horizontal/Vertical down-scaling factor Video image Horizontal/Vertical down-scaling factor LCD FIFOs control register LCD FIFOs status LCD FIFO1 parameters LCD FIFO2 parameters LCD FIFO1 transfer start address register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 513 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 LCDC Control Register Map, continued REGISTER NAME ADDRESS R/W DESCRIPTION RESET VALUE FIFO2SADDR FIFO1DREQCNT FIFO2DREQCNT FIFO1CURADR FIFO2CURADR LUTENTRY1 LUTENTRY2 LUTENTRY3 LUTENTRY4 TMDDITHP1 TMDDITHP2 TMDDITHP3 TMDDITHP4 TMDDITHP5 TMDDITHP6 TMDDITHP7 DDISPCP DISPWINS DISPWINE OSDWINS OSDWINE 0xFFF0_8034 0xFFF0_8038 0xFFF0_803C 0xFFF0_8040 0xFFF0_8044 0xFFF0_8060 0xFFF0_8064 0xFFF0_8068 0xFFF0_806C 0xFFF0_8070 0xFFF0_8074 0xFFF0_8078 0xFFF0_807C 0xFFF0_8080 0xFFF0_8084 0xFFF0_8088 0xFFF0_8090 0xFFF0_8094 0xFFF0_8098 0xFFF0_809C 0xFFF0_80A0 R/W R/W R/W R R R/W R/W R/W R/W R/W RW R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD FIFO2 transfer start address register FIFO1 data request transfer count register FIFO2 data request transfer count register FIFO1 current access address FIFO2 current access address TFT: lookup table entry index register TFT: lookup table entry index register TFT: lookup table entry index register TFT: lookup table entry index register Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Gray level dithered data duty pattern Dummy Display Color Pattern Register Valid Display Window Starting Coordinate Register Valid Display Window Ending Coordinate Register OSD Window Starting Coordinate Register OSD Window Ending Coordinate Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0101_0001 0x1111_0841 0x4949_2491 0x5555_52a5 0xB6B6_B556 0xEEEE_DB6E 0xFEFE_EFBE 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 514 - W90P710 LCDC Control Register Map, continued REGISTER NAME ADDRESS R/W DESCRIPTION RESET VALUE OSDOVCN OSDKYP OSDKYM LCDTCON1 LCDTCON2 LCDTCON3 LCDTCON4 LCDTCON5 LCDTCON6 BIST Look-Up SRAM Table 0xFFF0_80A4 0xFFF0_80A8 0xFFF0_80AC 0xFFF0_80B0 0xFFF0_80B4 0xFFF0_80B8 0xFFF0_80BC 0xFFF0_80C0 0xFFF0_80C4 0xFFF0_80D0 0xFFF0_8100 ..... 0xFFF0_8400 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W OSD Overlay Control Register OSD Overlay Color-Key Pattern OSD Overlay Color-Key Mask LCD Timing Control Register1 LCD Timing Control Register2 LCD Timing Control Register3 LCD Timing Control Register4 LCD Timing Control Register5 LCD Timing Control Register6 LCD SRAM Build In Self Test Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined Audio Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_CON ACTL_RESET ACTL_RDSTB 0xFFF0_9000 0xFFF0_9004 0xFFF0_9008 R/W Audio controller control register R/W Sub block reset control register R/W 0x0000_0000 0x0000_0000 DMA destination base address 0x0000_0000 register for record DMA destination length register for 0x0000_0000 ACTL_RDST_LENGTH 0xFFF0_900C R/W record DMA destination current address ACTL_RDSTC 0xFFF0_9010 R 0x0000_0000 register for record ACTL_RSR ACTL_PDSTB 0xFFF0_9014 0xFFF0_9018 R/W R/W Record status register 0x0000_0000 DMA destination base address 0x0000_0000 register for play DMA destination length register for 0x0000_0000 ACTL_PDST_LENGTH 0xFFF0_901C R/W play DMA destination current address ACTL_PDSTC 0xFFF0_9020 R 0x0000_0000 register for play ACTL_PSR ACTL_IISCON ACTL_ACCON 0xFFF0_9024 0xFFF0_9028 R/W Play status register 0x0000_0004 0x0000_0000 0x0000_0000 R/W IIS control register 0xFFF0_902C R/W AC-link control register - 515 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Audio Control Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACOS0 ACTL_ACOS1 ACTL_ACOS2 ACTL_ACIS0 ACTL_ACIS1 ACTL_ACIS2 0xFFF0_9030 R/W AC-link out slot 0 0xFFF0_9034 R/W AC-link out slot 1 0xFFF0_9038 R/W AC-link out slot 2 0xFFF0_903 C 0xFFF0_9040 0xFFF0_9044 R R R AC-link in slot 0 AC-link in slot 1 AC-link in slot 2 0x0000_0000 0x0000_0080 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Cache Controller Test Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CTEST0 CTEST1 0xFFF6_0000 R/W 0xFFF6_0004 R Cache test register 0 Cache test register 1 0x0000_0000 0x0000_0000 UART0 Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART0_RBR 0xFFF8_0000 UART0_THR 0xFFF8_0000 R W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Line Status Register Time Out Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x6060_6060 0x0000_0000 UART0_IER 0xFFF8_0004 R/W UART0_DLL 0xFFF8_0000 R/W UART0_DLM 0xFFF8_0004 R/W UART0_IIR 0xFFF8_0008 R W R R UART0_FCR 0xFFF8_0008 UART0_LSR 0xFFF8_0014 UART0_TOR 0xFFF8_001C UART0_LCR 0xFFF8_000C R/W - 516 - W90P710 High Speed UART1 Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART1_RBR UART1_THR UART1_IER UART1_DLL UART1_DLM UART1_IIR UART1_FCR UART1_LCR UART1_MCR UART1_LSR UART1_MSR UART1_TOR 0xFFF8_0100 0xFFF8_0100 0xFFF8_0104 0xFFF8_0100 0xFFF8_0104 0xFFF8_0108 0xFFF8_0108 0xFFF8_010C 0xFFF8_0110 0xFFF8_0114 0xFFF8_0118 0xFFF8_011C R W R/W R/W R/W R W R/W R/W R R R R/W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register UART1 Bluetooth Control Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060.6060 0x0000_0000 0x0000_0000 0x0000_0000 UART1_UBCR 0xFFF8_0120 UART2 Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART2_RBR 0xFFF8_0200 UART2_THR 0xFFF8_0200 UART2_IER R W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register IrDA Control Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 0x0000_0040 0xFFF8_0204 R/W UART2_DLL 0xFFF8_0200 R/W UART2_DLM 0xFFF8_0204 R/W UART2_IIR 0xFFF8_0208 R W UART2_FCR 0xFFF8_0208 UART2_LCR 0xFFF8_020C R/W UART2_MCR 0xFFF8_0210 R/W UART2_LSR 0xFFF8_0214 UART2_MSR 0xFFF8_0218 UART2_TOR 0xFFF8_021C R R R UART2_IRCR 0xFFF8_0220 R/W - 517 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 UART3 Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART3_RBR 0xFFF8_0300 UART3_THR 0xFFF8_0300 UART3_IER R W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 0xFFF8_0304 R/W UART3_DLL 0xFFF8_0300 R/W UART3_DLM 0xFFF8_0304 R/W UART3_IIR 0xFFF8_0308 R W UART3_FCR 0xFFF8_0308 UART3_LCR 0xFFF8_030C R/W UART3_MCR 0xFFF8_0310 R/W UART3_LSR 0xFFF8_0314 UART3_MSR 0xFFF8_0318 UART3_TOR 0xFFF8_031C Timer Control Registers Map REGISTER ADDRESS R/W R R R DESCRIPTION RESET VALUE TCR0 TCR1 TICR0 TICR1 TDR0 TDR1 TISR WTCR 0xFFF8_1000 0xFFF8_1004 0xFFF8_1008 0xFFF8_1010 0xFFF8_1014 0xFFF8_1018 R/W R/W R/W R R R/C Timer Control Register 0 Timer Control Register 1 Timer Initial Control Register 0 Timer Initial Control Register 1 Timer Data Register 0 Timer Data Register 1 Timer Interrupt Status Register Watchdog Timer Control Register 0x0000_0005 0x0000_0005 0x0000_00FF 0x0000_00FF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF8_100C R/W 0xFFF8_101C R/W - 518 - W90P710 AIC Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 AIC_SCR2 AIC_SCR3 AIC_SCR4 AIC_SCR5 AIC_SCR6 AIC_SCR7 AIC_SCR8 AIC_SCR9 AIC_SCR10 AIC_SCR11 AIC_SCR12 AIC_SCR13 AIC_SCR14 AIC_SCR15 0xFFF8_2004 0xFFF8_2008 0xFFF8_2010 0xFFF8_2014 0xFFF8_2018 0xFFF8_2020 0xFFF8_2024 0xFFF8_2028 0xFFF8_2030 0xFFF8_2034 0xFFF8_2038 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Source Control Register 1 Source Control Register 2 Source Control Register 3 Source Control Register 4 Source Control Register 5 Source Control Register 6 Source Control Register 7 Source Control Register 8 Source Control Register 9 Source Control Register 10 Source Control Register 11 Source Control Register 12 Source Control Register 13 Source Control Register 14 Source Control Register 15 Source Control Register 16 Source Control Register 17 Source Control Register 18 Source Control Register 19 Source Control Register 20 Source Control Register 21 Source Control Register 22 Source Control Register 23 Source Control Register 24 Source Control Register 25 Source Control Register 26 Source Control Register 27 Source Control Register 28 Source Control Register 29 Source Control Register 30 Source Control Register 31 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0xFFF8_200C R/W 0xFFF8_201C R/W 0xFFF8_202C R/W 0xFFF8_203C R/W AIC_SCR16 0xFFF8_2040 R/W AIC_SCR17 0xFFF8_2044 R/W AIC_SCR18 0xFFF8_2048 R/W AIC_SCR19 0xFFF8_204C R/W AIC_SCR20 0xFFF8_2050 R/W AIC_SCR21 0xFFF8_2054 R/W AIC_SCR22 0xFFF8_2058 R/W AIC_SCR23 0xFFF8_205C R/W AIC_SCR24 0xFFF8_2060 R/W AIC_SCR25 0xFFF8_2064 R/W AIC_SCR26 0xFFF8_2068 R/W AIC_SCR27 0xFFF8_206C R/W AIC_SCR28 0xFFF8_2070 R/W AIC_SCR29 0xFFF8_2074 R/W AIC_SCR30 0xFFF8_2078 R/W AIC_SCR31 0xFFF8_207C R/W - 519 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 AIC Control Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_IRSR AIC_IASR AIC_ISR AIC_IPER AIC_ISNR AIC_IMR AIC_OISR AIC_MECR AIC_MDCR AIC_SSCR AIC_SCCR AIC_EOSCR 0xFFF8_2100 0xFFF8_2104 0xFFF8_2108 0xFFF8_210C 0xFFF8_2110 0xFFF8_2114 0xFFF8_2118 0xFFF8_2120 0xFFF8_2124 0xFFF8_2128 0xFFF8_212C 0xFFF8_2130 0xFFF8_2200 R R R R R R R W W W W W W Interrupt Raw Status Register Interrupt Active Status Register Interrupt Status Register Interrupt Priority Encoding Register Interrupt Source Number Register Interrupt Mask Register Output Interrupt Status Register Mask Enable Command Register Mask Disable Command Register Source Set Command Register Source Clear Command Register End of Service Command Register ICE/Debug mode Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined Undefined Undefined Undefined Undefined Undefined AIC_TEST GPIO Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG0 GPIO_DIR0 GPIO_DATAIN0 GPIO_CFG1 GPIO_DIR1 GPIO_DATAIN1 GPIO_CFG2 GPIO_DIR2 GPIO_DATAIN2 GPIO_CFG3 GPIO_DIR3 GPIO_DATAIN3 0xFFF8_3000 R/W 0xFFF8_3004 R/W 0xFFF8_300C R 0xFFF8_3010 R/W 0xFFF8_3014 R/W 0xFFF8_301C R 0xFFF8_3020 R/W 0xFFF8_3024 R/W 0xFFF8_302C R 0xFFF8_3030 R/W 0xFFF8_3034 R/W 0xFFF8_303C R GPIO port0 configuration register GPIO port0 direction control register GPIO port0 data output register GPIO port0 data input register GPIO port1 configuration register GPIO port1 direction control register GPIO port1 data output register GPIO port1 data input register GPIO port2 configuration register GPIO port2 direction control register GPIO port2 data output register GPIO port2 data input register GPIO port3 configuration register GPIO port3 direction control register GPIO port3 data output register GPIO port3 data input register 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_5555 0x0000_0000 0x0000_0000 0xXXXX_XXXX GPIO_DATAOUT0 0xFFF8_3008 R/W GPIO_DATAOUT1 0xFFF8_3018 R/W GPIO_DATAOUT2 0xFFF8_3028 R/W GPIO_DATAOUT3 0xFFF8_3038 R/W - 520 - W90P710 GPIO Control Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG4 GPIO_DIR4 GPIO_DATAIN4 GPIO_CFG5 GPIO_DIR5 GPIO_DATAIN5 GPIO_CFG6 GPIO_DIR6 GPIO_DATAIN6 GPIO_XICFG GPIO_XISTATUS 0xFFF8_3040 R/W 0xFFF8_3044 R/W 0xFFF8_304C R 0xFFF8_3050 R/W 0xFFF8_3054 R/W 0xFFF8_305C R 0xFFF8_3060 R/W 0xFFF8_3064 R/W 0xFFF8_306C R 0xFFF8_3074 R/W 0xFFF8_3078 R/W GPIO port4 configuration register GPIO port4 direction control register GPIO port4 data output register GPIO port4 data input register GPIO port5 configuration register GPIO port5 direction control register GPIO port5 data output register GPIO port5 data input register GPIO port6 configuration register GPIO port6 direction control register GPIO port6 data output register GPIO port6 data input register GPIO input debounce control register Extend Interrupt Configure Register Extend Interrupt Status Register 0x0015_5555 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0xXXXX_XXX0 0xXXXX_XXX0 GPIO_DATAOUT4 0xFFF8_3048 R/W GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO_DATAOUT6 0xFFF8_3068 R/W GPIO_DBNCECON 0xFFF8_3070 R/W RTC Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_INIR RTC_AER RTC_FCR RTC_TLR RTC_CLR RTC_TSSR RTC_DWR RTC_TAR RTC_CAR RTC_LIR RTC_RIER RTC_RIIR RTC_TTR 0xFFF8_4000 R/W RTC Initiation Register 0xFFF8_4004 R/W RTC Access Enable Register 0xFFF8_4008 R/W RTC Frequency Compensation Register 0xFFF8_400C R/W Time Loading Register 0xFFF8_4010 R/W Calendar Loading Register 0xFFF8_4014 R/W Time Scale Selection Register 0xFFF8_4018 R/W Day of the Week Register 0xFFF8_401C R/W Time Alarm Register 0xFFF8_4020 R/W Calendar Alarm Register 0xFFF8_4024 R Leap year Indicator Register 0xFFF8_4028 R/W RTC Interrupt Enable Register 0xFFF8_402C R/C RTC Interrupt Indicator Register 0xFFF8_4030 R/W RTC Tick Time Register 0x0000_0000 0x0000_0700 0x0000_0000 0x0005_0101 0x0000_0001 0x0000_0006 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 521 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Smart card Host Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE Smartcard Host Interface 0 SCHI_RBR0 SCHI_TBR0 SCHI_IER0 SCHI_ISR0 SCHI_SCFR0 SCHI_SCCR0 SCHI_CBR0 SCHI_SCSR0 SCHI_GTR0 SCHI_ECR0 SCHI_TMR0 SCHI_TOC0 0xFFF8_5000(BDLAB=0) 0xFFF8_5000 (BDLAB=0) 0xFFF8_5008 (BDLAB=0) 0xFFF8_5008 (BDLAB=0) 0xFFF8_500C 0xFFF8_5010 0xFFF8_5014 0xFFF8_5018 0xFFF8_501C 0xFFF8_5020 0xFFF8_5028 R Receiver Buffer Register Undefined Undefined 0x0000_0080 0x0000_00C1 0x0000_0000 0x0000_0010 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 W Transmitter Buffer Register R Interrupt Status Register 0xFFF8_5004 (BDLAB=0) R/W Interrupt Enable Register W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 SCHI_TOIR0_0 0xFFF8_502C SCHI_TOIR1_0 0xFFF8_5030 SCHI_TOIR2_0 0xFFF8_5034 SCHI_TOD0_0 SCHI_TOD1_0 SCHI_TOD2_0 SCHI_BTOR_0 SCHI_BLL_0 SCHI_BLH_0 SCHI_ID_0 SCHI_RBR1 SCHI_TBR1 SCHI_IER1 SCHI_ISR1 SCHI_SCFR1 SCHI_SCCR1 0xFFF8_5038 0xFFF8_503C 0xFFF8_5040 0xFFF8_5044 R/W Buffer Time out Data Register 0xFFF8_5000 (BDLAB=1) R/W 0xFFF8_5004 (BDLAB=1) R/W 0xFFF8_5008 (BDLAB=1) 0xFFF8_5800 (BDLAB=0) 0xFFF8_5800 (BDLAB=0) 0xFFF8_5808 (BDLAB=0) 0xFFF8_5808 (BDLAB=0) 0xFFF8_580C R R Baud Rate Divisor Latch Lower 0x0000_001F Byte Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register Receiver Buffer Register 0x0000_0070 Undefined Undefined 0x0000_0080 0x0000_00C1 0x0000_0000 0x0000_0010 Smartcard Host Interface 1 W Transmitter Buffer Register R Interrupt Status Register 0xFFF8_5804 (BDLAB=0) R/W Interrupt Enable Register W Smart card FIFO Control Register R/W Smart card Control Register - 522 - W90P710 Smart card Host Control Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_CBR1 SCHI_SCSR1 SCHI_GTR1 SCHI_ECR1 SCHI_TMR1 SCHI_TOC1 SCHI_TOIR0_1 SCHI_TOIR1_1 SCHI_TOIR2_1 SCHI_TOD0_1 SCHI_TOD1_1 SCHI_TOD2_1 SCHI_BTOR1 SCHI_BLL1 SCHI_BLH1 SCHI_ID1 0xFFF8_5810 0xFFF8_5814 0xFFF8_5818 0xFFF8_581C 0xFFF8_5820 0xFFF8_5828 0xFFF8_582C 0xFFF8_5830 0xFFF8_5834 0xFFF8_5838 0xFFF8_583C 0xFFF8_5840 0xFFF8_5844 0xFFF8_5800 (BDLAB=1) 0xFFF8_5804 (BDLAB=1) 0xFFF8_5808 (BDLAB=1) R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF R/W Buffer Time out Data Register 0x0000_0000 Baud Rate Divisor Latch Lower R/W 0x0000_001F Byte Register Baud Rate Divisor Latch Higher R/W 0x0000_0000 Byte Register R Smart Card ID Number Register 0x0000_0070 I2C Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C Interface 0 I2C_CSR0 I2C_DIVIDER0 I2C_CMDR0 I2C_SWR0 I2C_RxR0 I2C_TxR0 I2C_CSR1 I2C_DIVIDER1 I2C_CMDR1 I2C_SWR1 I2C_RxR1 I2C_TxR1 0xFFF8_6000 0xFFF8_6004 0xFFF8_6008 0xFFF8_600C 0xFFF8_6010 0xFFF8_6014 0xFFF8_6000 0xFFF8_6004 0xFFF8_6008 0xFFF8_600C 0xFFF8_6010 0xFFF8_6014 R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W I2C0 Control and Status Register I2C0 Clock Prescale Register I2C0 Command Register I2C0 Software Mode Control Register I2C0 Data Receive Register I2C0 Data Transmit Register I2C Interface 1 I2C1 Control and Status Register I2C1 Clock Prescale Register I2C1 Command Register I2C1 Software Mode Control Register I2C1 Data Receive Register I2C1 Data Transmit Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 - 523 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 USI Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL USI_DIVIDER USI_SSR Reserved USI_Rx0 USI_Rx1 USI_Rx2 USI_Rx3 USI_Tx0 USI_Tx1 USI_Tx2 USI_Tx3 0xFFF8_6200 R/W 0xFFF8_6204 R/W 0xFFF8_6208 R/W 0xFFF8_620C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C N/A R R R R W W W W Control and Status Register Clock Divider Register Slave Select Register Reserved Data Receive Register 0 Data Receive Register 1 Data Receive Register 2 Data Receive Register 3 Data Transmit Register 0 Data Transmit Register 1 Data Transmit Register 2 Data Transmit Register 3 0x0000_0004 0x0000_0000 0x0000_0000 N/A 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 PWM Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR PWM_CSR PWM_PCR PWM_CNR0 PWM_CMR0 PWM_PDR0 PWM_CNR1 PWM_CMR1 PWM_PDR1 PWM_CNR2 PWM_CMR2 PWM_PDR2 PWM_CNR3 PWM_CMR3 PWM_PDR3 PWM_PIER PWM_PIIR 0xFFF8_7000 0xFFF8_7004 0xFFF8_7008 0xFFF8_700C 0xFFF8_7010 0xFFF8_7014 0xFFF8_7018 0xFFF8_701C 0xFFF8_7020 0xFFF8_7024 0xFFF8_7028 0xFFF8_702C 0xFFF8_7030 0xFFF8_7034 0xFFF8_7038 0xFFF8_703C 0xFFF8_7040 R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/C PWM Prescaler Register PWM Clock Select Register PWM Control Register PWM Counter Register 0 PWM Comparator Register 0 PWM Data Register 0 PWM Counter Register 1 PWM Comparator Register 1 PWM Data Register 1 PWM Counter Register 2 PWM Comparator 2 PWM Data Register 2 PWM Counter Register 3 PWM Comparator Register 3 PWM Data Register 3 PWM Interrupt Enable Register PWM Interrupt Indication Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 524 - W90P710 KPI Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPICONF 0xFFF8_8000 R/W Keypad controller configuration Register 0x0000_0000 KPI3KCONF 0xFFF8_8004 R/W Keypad controller 3-keys configuration register 0x0000_0000 KPILPCONF 0xFFF8_8008 R/W Keypad controller low power configuration 0x0000_0000 register KPISTATUS 0xFFF8_800C R/O PS2 Control Register Map REGISTER ADDRESS R/W/C DESCRIPTION RESET VALUE Keypad controller status register 0x0000_0000 PS2CMD PS2STS 0xFFF8_9000 0xFFF8_9004 R/W R/W RO RO PS2 Host Controller Command Register PS2 Host Controller Status Register 0x0000_0000 0x0000_0000 PS2SCANCODE 0xFFF8_9008 PS2ASCII 0xFFF8_900C PS2 Host Controller RX Scan Code 0x0000_0000 Register PS2 Host Controller RX ASCII Code 0x0000_0000 Register - 525 - Publication Release Date: January 17, 2005 Revision A.2 W90P710 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 526 - |
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